Many enhancements have also been included in CR-5000 Lightning, the company's leading high-speed design verification tool that enables rapid, accurate results, coupled with first-rate signal integrity, EMC and power integrity analysis. Within CR-5000 Lightning, designers can automatically derive total routing capacitance to meet vendor specification for high-speed applications, such as DDR3. Lightning also has support for nested sub-circuits and coupled inductors (K elements) for importing SPICE models.
This offers users more capability and power for analysis. For batch SI simulation and analysis, improvements in operation and reporting for Lightning’s SI Controller include: expanded verification results and new options for generating reports, including automatic waveform image creation, to improve verification during the design process.
Also included are enhancements to DDR2/DDR3 wizards for managing constraints for multi-receiver, high-speed signal structures, and enhanced design reports supporting cross-probing with the PCB design. Constraint setup is now simpler: differential pairs can be created automatically, and new utilities allow constraints to be applied to high-speed signals without accessing the Constraint Editor. There is also improved collaboration during layout and design review. Design mark-ups can be exchanged bi-directionally between Board Designer and Board Viewer Advance for intelligent exchange of feedback.
For improved co-design of PCBs and programmable devices, such as FPGAs and ASICs, there is now tighter integration in CR-5000 with Zuken’s Graphical Pin Manager (GPM). New changes to high pin count, multi-symbol devices in GPM can be updated collectively and automatically during logical circuit design. For FPGA design, pin constraint files in vendor specific formats, such as Xilinx or Altera, can submitted to FPGA design tools, while updated signals associated to a device pin or signal names can be filtered. Other improvements include new filter options to control attributes while exporting pin-out information for better IP control during ASIC development.
