Abstract: In order to study the electromagnetic compatibility problems caused by the clock PCB circuit boards, using the method of numerical simulation, electromagnetic compatibility design of the clock circuit when several major influencing factors analysis to determine the design of the PCB circuit boards the clock selection principles and specific objects EMC clock circuit design and content, and by optimizing the clock design layout and routing to achieve improved PCB board EMC design. Finally, the clock can be effectively cut off the PCB interference pathways several measures for the engineering and technical personnel to provide a solution to issues relate
Keywords: PCB board; clock signal; electromagnetic compatibility design; numerical simulation
Introduction
As we all know, the three elements of EMC electromagnetic interference source, pathway was interfering objects and dissemination of electromagnetic interference. Clock signal PCB board installed is a problem caused by the PCB EMC common and very important source of radiation. Although the clock signal and other data signals, control logic level signals are generally the same, the turnover rate generally is not much difference (than most bus data rate and the turnover rate of the clock signal is 1:1 or 1:2 ), but the reason for easier access to the clock signal or radiation emission limits over, mainly due to the clock signal is relatively strictly periodic signal in the frequency domain energy focused on some frequency, and the data signal is an periodic signal in the frequency domain energy is relatively scattered. Therefore, a good clock circuit design is the key tohe PCB EMC design
1 the clock signal spectrum
According to Fourier expansion can be, A range for A, the cycle for T, pulse width is t0, up and down time for tr trapezoidal clock waveforms, the harmonics in the n harmonic components as:
Type C (n) for n times harmonics of harmonic component, unit: V or dB u V. Fourier series of trapezoidal clock waveforms from above you can see, the factors influencing the clock signal radiation intensity has A clock waveform amplitude and duty ratio (t0 + tr) T/T, the clock cycle (f) or the clock frequency, and the rise time and fall time of the clock waveform. The amplitude of the clock signal is related to its direct linear interferences, rising and falling time on the clock is very important to the influence of high harmonics.
2.Factors influencing the spectrum clock
2.1 Effect of radiation clock rise time
Suppose there are two clock signals are amplitude 1 V, frequencies of 50 MHz, respectively 2 ns rise time and 4 ns. Can be obtained according to the above spectral distribution of the Fourier transform of the two clock signals shown in Figure 1.
2.2 clock frequency of radiation
Hypothesis has 2 clock signal, amplitude of 1 V, rise time of 3.33 ns, repetition frequency of 30 MHz and 90 MHz, according to the Fourier transform can get above 2 clock signal spectrum distribution, as shown in figure 2 and figure 3.
2.3 The comparison of the clock frequency spectrum
Can be seen from the figure 1, the clock of harmonic interference, especially the higher harmonic interference intensity decreases as the rising and falling time and strengthen greatly, 2 ns rise higher harmonic asked the clock than 4 ns rise time of 1 ~ 2 times higher than that of corresponding harmonic.
When up and down the time phase, at the same time period T (or fundamental frequency f) on the higher harmonic distortion created by the clock is very large, the influence of figure 2 and figure 3 are repeated frequency of 30 MHZ and 90 MHZ, 3.33 ns rise time, amplitude of 1 V trapezoidal clock the size of the harmonic wave interference. Can be seen from the graph, the two clocks in the harmonic interference, 270 MHz to 90 MHz clock in 270 MHz (3 harmonics) harmonic interference than 30 MHz clock in 270 MHz (9 harmonics) about 15 dB higher than that of harmonic interference; To compare 90 MHz clock in 810 MHz (9 harmonics) harmonic interference than 30 MHz clock in 810 MHz (27 times harmonic) around 12 dB higher than that of harmonic interference.
So when the clock system design, in conditions allow preferable lower clock frequency, such as in the design of Ethernet PHY chip with a 125 MHz clock and adoption of 25 MHz external clock, if choose in other technical conditions permit should first external clock for 25 MHz chip, and technical conditions are met in all aspects of choice under the condition of rising and falling time longer clock or clock driver circuit.
3 clock circuit of the electromagnetic compatibility design
On the PCB board clock electromagnetic compatibility design of the circuit is mainly from the following several aspects to consider: clock crystals and drive power handling; Below the crystals in the PCB and its drive do local copper clad processing; The clock signal wiring; Termination of the clock signal and filter, etc.
3.1 the power supply design
The clock circuit output state transformation occurs at the same time, the power supply system to produce larger transient current, or current, in order to avoid the clock chip veneer the impact of the power supply system, single power supply of electromagnetic interference suppression, you need to part of the clock power filtering and isolation design. Its design principle diagram as shown in figure 4.
3.2 copper and layout design
Internal crystal oscillator circuit generates the RF current, if the crystal is a metal enclosure, the DC power supply pin is a DC voltage reference and an internal RF current loop crystal reference basis. Different crystals (CMOS, TTL, ECL, etc.) generated inside the metal shell of the RF current radiation of different sizes, if the crystal is not connected with the large metal ground plane, you can not be on crystal metal casing put large transient currents diarrhea to the ground plane.
Oscillator and clock circuitry in the local ground plane below the crystal and associated circuitry can be internally generated common mode RF current is supplied path, so that the minimum RF transmitter. In order to withstand the flow of partially plane mode RF currents need to be partially in the system plane and the other is connected to multi-point ground plane. I.e. locally within the system ground plane connected to the plane surface of the via to provide a low impedance to ground. Also note that to ensure the integrity of the ground underneath the crystal plane. Use the full ground plane signal and the signal itself reflux opposite direction, the same size, can cancel each other well, you can ensure good signal integrity and electromagnetic compatibility characteristics. However, if the ground plane is not complete, the current return path of the signal currents cancel each other when not in itself (although this is sometimes unavoidable current imbalance), the portion of the common mode current is generated. Common-mode voltage generated by the external structure will inspire connection, resulting in greater radiation.
If the wiring from below through the crystal, especially the noise transmitted to the connector wiring, not only undermine the role of the local ground plane, but also the crystal produced by capacitive coupling coupled way to pass through the signal line below it, so These signal lines with a common-mode voltage noise, if the signal line extends through the connector and PCB, it will bring out the noise. This is a typical common-mode radiation, the principle shown in Figure 5.
3 EMC design clock circuit
3.3 Termination Design
Clock driver chip unused output pin , such as: load ( open circuit ) , due to the pin open reflection may cause electromagnetic interference clock higher harmonics . In a single board plus spare termination is a solution to this problem, but the use of alternate terminating resistors or capacitors or other termination methods mainly depends on the frequency load caused by electromagnetic interference. If a resistive termination , we must consider the power consumption and the resulting drive drive current ; If capacitive termination , may increase the frequency of some other electromagnetic interference , so to optimize the size of the capacitor capacitance value when ; If you do not pin is not terminated , but already there is sufficient margin proved by tests of electromagnetic interference , there is no need for additional spare termination is not treated with the pin .
Below 3807 digital clock chip, for example , with the results of simulation experiments to explain the role of backup terminated . Figure 6 to Figure 8 shows the output pins when the chip is not in the open , then 50 Ω resistor to ground , then 75 Ω resistor to ground , then when the 20 pF capacitance to ground , etc., current driver of the foot, the spectral distribution and drive the current generated by electromagnetic radiation.
As can be seen from the above results:
(1) The minimum drive current open circuit, but there are obvious narrow pulse ringing. If you do not have to explain the drive pin load (open circuit), the drive's power consumption is minimized. Thus it will bring an unfavorable aspect, the drive current that is high frequency spectral components becomes large, high-frequency electromagnetic interference may cause a problem. And electromagnetic interference spectrum by this curve in Figure 7 and Figure 8 in an open driving current (blue curve) can be verified
(2) if the drive without pin with resistance butt, drive current get bigger, but the drive current ringing decreased significantly. The termination of the small resistance is proposed, which can improve the drive current ringing, but increase the drive current, power consumption become bigger; If the big resistance butt, can reduce the drive current, but will make the drive current ringing (termination of a limit) resistance is open. Through the simulation results, choose 75 ohm termination resistor on the one hand can make the drive current will not very big, on the other hand drive current ring is not very obvious.
(3) if the drive without pin USES capacitance termination, drive current peak, at the same time, drive current pulse width is bigger. This means low frequency component of drive current will significantly bigger, this is about to pay attention to the low frequency harmonic electromagnetic interference problem. Figure 7 and figure 8 corresponding capacitance in the termination of the drive current spectrum curve and curve of low frequency component of the electromagnetic interference significantly larger also verified this problem.
4 conclusion
This paper is about how to decrease the disturbance of the clock (source) are analyzed and summarized, therefore can draw the conclusion of how to cut off the clock under the interference of transmission. Clock circuit is a fundamental wave and harmonic energy maximum constraint to the specified range (required for the energy transmission circuit surrounding area as small as possible). The second is effective to establish the clock circuit area and the isolation of input and output interface circuit. Thus when the clock circuit design layout and wiring to achieve the purpose of optimizing the electromagnetic compatibility design.
