A digital logic circuit consists of a collection of interconnected parts. Most parts are integrated circuits, but in practical designs there are usually a number of passive components and connectors. Each part has one or more pins, which are terminals at which electrical connections are made. Integrated circuits may have hundreds of pins on a single package. The pins are interconnected by nets. Each net is a collection of pins that must be electrically interconnected in the final realization. A circuit board is built as a stack of layer pairs. Each pair starts as an insulating sheet with copper deposited on one or both sides. The copper sides of the sheet are first etched with different wiring pat-terns. Then the sheets are stacked into a sandwich separated by insulating material.
Small holes are drilled into the board. Finally, the holes are plated with metal, so that electrical contact is made with each layer that has copper left at the hole location. This means that a hole can form a conductive path between two or more layers called a via. There are two ways of attaching parts to boards. The current industry standard is to solder the pins into a via pattern in the circuit board1. The solder connects the pin to any layers that have metal pads at the via locations. This method is simple and reliable, but does not allow the pins to be packed very closely. Spacings of 100 mils (thousandths of an inch) are common for through-hole pins. The second newer method is surface mounting.
In this technique, the pins are flat strips that are soldered to the surface of the board without penetrating it. Surface mounting allows increased pin density, and so larger numbers of pins for a given package size. Surface mounting also leads to a harder routing problem, but not one that is qualitatively different. In the body of this report, only through-hole pins will be considered, and surface mounting will be revisited in the Limitations section.
For our purposes, the term via will mean either a hole that connects two or more signal layers, or a hole that connects a pin of a part to one or more signal layers. In all but the simplest printed circuit boards, the nets that interconnect the pins of chips are divided into two classes. A small number are singled out for special treatment as power nets. These supply power and ground to the parts on the board, and nearly every part will be connected to at least two of them. Because a power net carries large currents, one or more layers of the circuit board are devoted entirely to it, and become power layers. It is not uncommon to have one power layer for each of the supply voltages, and several for ground. In multi-layer circuit boards, often half of the copper layers are reserved for power and ground. The etching pattern for power layers is simple. The layer is left as solid copper except at pin and via locations that are not to be connected to the power net.
At these locations, a small disk is etched away so that no electrical contact will be made during drilling and plating. Figure 22 on page 25 shows an ex-ample of a power layer. The generation of power layer patterns is straightforward once the complete pattern of vias is known. More details are given in the appendix. The remainder of the nets are signal nets, which carry the digital logic values. These connect to far fewer pins than the power nets and have small current flows, but there are thousands of them.
Signal nets are routed on the remaining signal layers by adding traces and vias to the circuit board. A trace is a thin wire lying entirely on one signal layer that is formed by etching away the surrounding metal. Figure 21 on page 24 shows a signal layer. Figure 1 shows actual board dimensions for an example process. In the figure, traces must be at least 8mils wide and at least 8 mils apart. Pads for vias must be 60 mils in diameter to allow for error in drilling and plating a 37 mil via.
