To provide PCB designers with an automated, intelligent planning and routing environment, semiconductor design tool leader Cadence Design is unveiling global route environment technology for its Allegro PCB design tools, which combines a graphical interconnect flow-planning architecture and a hierarchically-aware global routing engine.
Prior to this technology, the company reminded that PCB designers spent weeks or months manually routing complex, high-speed designs with many interconnected buses and multiple high pin-count devices, resulting in prolonged and unpredictable design-cycle time, impacting project schedules and budgets.
To bring intelligent automation where no automation was previously available, Cadence said it worked with several early adopter partners, including Motorola, to help define the problem as well as drive and validate this unique solution.
Jeff Underwood, principal staff printed circuit designer at Motorola said in a statement, “By utilizing this new, enhanced routing environment, Motorola is enabling our engineers and designers to more accurately convey design intent, throughout the entire routing design process.”
Further, Cadence says PCB designers have long sought a PCB environment that comprehends the global nature of the design in an environment that captures their design intent, provides decision feedback, and then intelligently and automatically performs design tasks adhering to their design intent.
Cadence’s global route environment technology aims to do exactly that with a graphical interconnect flow planning architecture that allows designers to create and define an intelligent abstraction of critical interfaces and capture interconnect design intent.
This environment also leverages the global routing engine that allows designers to combine their knowledge and design intent with a hierarchical view of the design to plan the best interconnect solution possible.
