PCB board testing machine the basic testing principle is ohm's law, the test method is to stay between the test point to add certain test voltage, selected by decoding circuit on the PCB under test points, get the resistance between two points corresponding to voltage signal, through the voltage comparison circuit, test the resistance between two points or on and off. Repeat the above steps for many times, can be realized to the entire circuit board test.
Because of the tested points is more, general test machine was above 2048 points, the test control circuit is more complex, the test point search method and switching methods directly affect the speed of testing machine test, this paper studies the hardware control system based on FPGA design.
The hardware control system
Testing process is under the control of computer, control test circuit switch on different test respectively. Testing machine system consists of the following sections: computer PC104, test control logic (by the FPGA implementation), high voltage test circuit. The upper machine is mainly completed the human-computer interaction, test algorithm, test data processing and control output, and other functions. The FPGA control high voltage test circuit to complete the test process of PCB.
This system by a PC104 as upper computer, the FPGA as the core, realize the control of PC to test through the PC104 bus.
Test system overall block diagram is shown in figure 1.
The FPGA with PC104 interface circuit
PC104 bus is a specially designed for embedded control definition of industrial control bus, the signal definition and ISA bus is basically the same. PC104 bus, a total of four kinds of bus cycle, that is, eight of the bus cycle, a 16-bit bus cycle, the DMA bus cycles, and refresh the bus cycle. 16 I/O bus cycles for three clock cycles, eight I/O bus cycles for 6 clock cycles. In order to improve the speed of communication, using 16-bit ISA bus communication mode, namely the 16 I/O mode. In order to make full use of the resources of PC104, expanded application of PC104 system bus on FPGA online configuration. Normal work by FPGA with PC104 bus data communication.
The FPGA and serial A/D and D/A device interface
According to the requirements of the testing machine system design requirements, the test voltage and reference voltage two channel self-inspection, namely A/D conversion channel at least three ways. Two way comparison reference voltage by D/A output circuit, the system of D/A channel requires two channel. In order to reduce the A/D and D/A control signal, choose the serial A/D and D/A devices. Comprehensive performance, price and other factors, choose the device for the TLC2543 A/D, D/A devices for TLV5618.
TLV5618 is TI company with reference input buffer (high impedance) dual 12 voltage output DAC, through CMOS compatible 3 line serial bus to realize digital control. Device receives commands A 16-bit word, produce two lines of D/A analog output. TLV5618 only A single I/O cycle, is determined by the external clock SCL K, 16 clock cycles, write on chip registers will command word, after the completion of the D/A conversion. TLV5618 read starts from the falling edge of CS and effective command word, starting from the falling edge of the SCLK next read in data, read in transformation period is entered namely after 16 bits of data, until the next time a falling edge of CS. Its operating sequence diagram is shown in figure 2.
TLC2543 is TI company with serial control and 11 12, switch at the input capacitance type successive approximation A/D converter. On chip converter has the characteristics of high speed, high precision and low noise. TLC2543 working process is divided into two cycles: the I/O cycle and the conversion cycle. I/O cycle is determined by the external clock SCLK, continuation of 8, 12 or 16 clock cycle, at the same time two kinds of operations: the SCLK rising along the 8 bits of data input in the MSB way to register within; Falling edge on the SCLK output 8, 12, 16 in the MSB way conversion results. Transformation period at the end of the I/O cycle a falling edge SCLK start, until the EOC high signal, instructs the conversion is complete. TLV5618 I/O cycle is consistent, in order to adopt the way of MSB, using CS 16 clock transmission sequence. Its operating sequence as shown in figure 3.
Since both devices is the SPI interface, the two devices can be connected to the same SPI bus, through different optional signals of different device operation. Due to the complexity of SPI interface protocol, and can be seen from the figure 3, the two components of temporal sequence does not use all of the SPI interface. In order to implement in accordance with the above logic sequence, decrease the standard SPI interface IP check the FPGA resources waste, design adopts the Verilog hardware description language used design method of synchronous state machine (FSM), write an ADC and DAC control sequence. Program is actually a nested state machine, by the main state machine and from the state machine by line to start the bus under the condition of different input signal form different functions of finite state machine. From figure 3, the D/A four state operation, A/D operation has seven states. Several state of the two state is the same, so the available A finite state machine to complete to the operation of the serial A/D and D/A. Program is actually a nested state machine, by the main state machine and from the state machine by controlling the bus started under the condition of different input signal is a different function more complex finite state machine. A/D and D/A share only driving clock (SCLK) and the data bus (SI, SO). Due to operating write cycle has 16 clock cycles, read cycle has 12 clock cycle, the module is in three nested finite state machine, the main state machine as shown in figure 4.
System design, AD, DA encapsulated into a separate module, operation is controlled by the upper output module and the control signal to start the command word this module to the corresponding operation, operation into a state (idle), after the completion of this module signal state corresponding to the upper module.
