Signal integrity (SI) refers to the quality of the signal on the signal line, that is, the ability of the signal to respond with the correct timing and voltage in the circuit. If the signal in the circuit can reach the receiver with the required timing, duration and voltage amplitude, then it can be determined that the circuit has better signal integrity. Conversely, when the signal does not respond properly, a signal integrity problem occurs.
With the use of high-speed devices and more and more high-speed digital system designs, the system data rate, clock rate, and circuit density are constantly increasing. In this design, the system's fast-slope transients and operating frequencies are high, and cables, interconnects, printed boards (PCBs), and silicon chips will exhibit very different behaviors from low-speed designs, namely signal integrity issues. Signal integrity problems can cause or directly bring such things as signal distortion, timing errors, incorrect data, addresses, control lines, and system errors, and even crash the system. This has become a very noteworthy issue in high-speed product design. This article first introduces the issue of PCB signal integrity, then explains the steps of PCB signal integrity, and finally introduces how to ensure PCB design signal integrity.
PCB signal integrity issues mainly include signal reflection, crosstalk, signal delay, and timing errors.
1. Reflection: When the signal is transmitted on the transmission line, when the characteristic impedance of the transmission line on the high-speed PCB does not match the source impedance or load impedance of the signal, the signal will be reflected, causing the signal waveform to overshoot, undershoot and the ringing phenomenon caused by it. Overshoot refers to the first peak (or bottom) of the signal transition. It is an additional voltage effect above the power supply level or below the reference ground level. Undershoot refers to the signal jump change to the next valley (or peak). Excessive overshoot voltage often impacts the device for a long period of time, causing damage to the device. Undershoot will reduce the noise margin. Ringing increases the time required for signal stabilization, which affects system timing.
2. Crosstalk: In PCB, crosstalk refers to the undesired noise interference caused by the electromagnetic energy through the mutual capacitance and mutual inductance coupling to the adjacent transmission line when the signal propagates on the transmission line. It is caused by interaction of different structures of the electromagnetic field in the same area. Mutual capacitance causes coupling current, which is called capacitive crosstalk; while mutual inductance causes coupling voltage, which is called inductive crosstalk. On the PCB, crosstalk is related to trace length, signal line spacing, and the condition of the reference ground plane.
3. Signal delay and timing error: The signal is transmitted at a limited speed on the wires of the PCB, and the signal is sent from the driver to the receiver, with a transmission delay in between. Excessive signal delays or mismatched signal delays can lead to timing errors and disrupted logic device functionality.
High-speed digital system design analysis based on signal integrity analysis can not only effectively improve product performance, but also shorten product development cycles and reduce development costs. With the development of digital systems toward high speed and high density, it is extremely urgent and necessary to master this design weapon. With the continuous improvement and improvement of signal integrity analysis models and calculation analysis algorithms, digital system design methods that use signal integrity for computer design and analysis will be widely and comprehensively applied.
1. Preparations before design
Before the design begins, you must first think and determine the design strategy so that you can guide tasks such as component selection, process selection, and cost control of circuit board production. As far as SI is concerned, it is necessary to carry out investigations in advance to form planning or design guidelines, so as to ensure that the design results do not show obvious SI problems, crosstalk or timing problems.
2. Stack-up of circuit boards
Some project teams have great autonomy in determining the number of PCB layers, while others do not have this autonomy, so it is important to know where you are.
Other important questions include: What is the expected manufacturing tolerance? What is the expected insulation constant on the board? What is the allowable error of line width and spacing? What is the allowable error in the thickness and spacing of the ground and signal layers? All this information can be used during the pre-wiring phase.
Based on the above data, you can choose stack-up. Note that almost every PCB inserted into another circuit board or backplane has a thickness requirement, and most circuit board manufacturers have a fixed thickness requirement for the different types of layers they can manufacture, which will greatly limit the number of final stack-up . You may want to work closely with the manufacturer to define the number of stack-up. Impedance control tools should be used to generate target impedance ranges for different layers, taking into account manufacturing tolerances provided by the manufacturer and the effects of adjacent wiring.
In the ideal case of complete signals, all high-speed nodes should be routed in the inner layer of impedance control (such as a stripline). To optimize SI and keep the board decoupled, you should route the ground / power planes in pairs as much as possible. If there can only be one pair of ground / power planes, you are the only one. If there is no power plane at all, you may encounter SI problems by definition. You may also encounter situations where it is difficult to simulate or emulate the performance of the board before the return path of the signal is undefined.
3. Crosstalk and impedance control
Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal lines. Analysis of the coupling of adjacent parallel signal lines may determine the "safe" or expected spacing (or parallel wiring length) between signal lines or between various types of signal lines. For example, if you want to limit the crosstalk between the clock and the data signal node to less than 100mV, but you need to keep the signal traces parallel, you can find the minimum allowable distance between signals on any given wiring layer through calculation or simulation. At the same time, if the design includes impedance-critical nodes (either clocks or dedicated high-speed memory architectures), you must place the wiring on one (or several) layers to get the desired impedance.
4. Important high-speed nodes
Delay and stagnant time are key factors that must be considered in clock routing. Because of the stringent timing requirements, such nodes often require termination devices to achieve the best SI quality. These nodes should be determined in advance, and the time required to adjust component placement and routing should be planned in order to adjust the pointers of the signal integrity design.
5. Technology selection
Different drive technologies are suitable for different tasks. Is the signal point-to-point or point-to-multiple tapped? Is the signal output from the board or is it left on the same board? What is the allowed time delay and noise margin? As a general rule for signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason for the 50MHZ clock to use 500PS rise time. A 2-3NS slew rate control device must be fast enough to ensure the quality of SI and help solve problems such as output synchronous switching (SSO) and electromagnetic compatibility (EMC).
In the new FPGA programmable technology or user-defined ASIC, you can find the superiority of the driving technology. With these custom (or semi-custom) devices, you have a lot of scope for choosing drive amplitude and speed. At the beginning of the design, it is necessary to meet the FPGA (or ASIC) design time requirements and determine the appropriate output selection, including pin selection if possible.
At this design stage, obtain the appropriate simulation model from the IC supplier. To effectively cover SI simulation, you will need an SI simulation program and a corresponding simulation model (possibly an IBIS model).
Finally, you should establish a series of design guidelines during the pre-wiring and routing stages, which include: target layer impedance, wiring pitch, preferred device technology, important node topology, and termination planning.
6.Pre-wiring stage
The basic process of pre-wiring SI planning is to first define the input parameter range (driving amplitude, impedance, tracking speed) and possible topological range (min / max length, short line length, etc.), and then run each possible simulation combination to analyze the timing and SI simulation results, and finally found an acceptable value range.
Next, the working range is interpreted as the wiring constraints for PCB routing. Different types of software tools can be used to perform this type of "cleaning" preparation, and the routing program can automatically handle this type of routing constraint. For most users, the timing information is actually more important than the SI results. The interconnect simulation results can change the wiring to adjust the timing of the signal path.
In other applications, this process can be used to determine the placement of pins or devices that are not compatible with the system timing pointer. At this point, it is possible to completely determine the nodes that need to be manually routed or the nodes that do not require termination. For programmable devices and ASICs, you can also adjust the output drive selection at this time in order to improve the SI design or avoid the use of discrete termination devices.
7, SI simulation after wiring
Generally speaking, it is difficult for SI design guidelines to ensure that there are no SI or timing problems after the actual wiring is completed. Even if the design is guided by a guide, unless you can continuously check the design automatically, there is no guarantee that the design will fully comply with the guidelines, and problems will inevitably occur. Post-wiring SI simulation checks will allow planned breaks (or changes) in design rules, but this is only necessary for cost considerations or stringent wiring requirements.
8. Post-manufacturing stage
Taking the above measures can ensure the SI design quality of the circuit board. After the circuit board is assembled, it is still necessary to place the circuit board on a test platform and use an oscilloscope or TDR (time domain reflectometer) to measure and compare the results of the real circuit board and simulation expectations. These measurements can help you improve your model and manufacturing parameters so that you can make better (less restrictive) decisions in your next predesign survey.
9. Model selection
There are many articles on model selection. Engineers performing static timing verification may have noticed that, although all the data can be obtained from the device data sheet, it is still difficult to build a model. The SI simulation model is just the opposite. The model is easy to build, but the model data is difficult to obtain. Essentially, the only reliable source of SI model data is the IC vendors, who must work in harmony with the design engineers. The IBIS model standard provides a consistent data carrier, but the establishment of the IBIS model and its quality assurance are costly. IC suppliers still need the driving force of market demand for this investment, and circuit board manufacturers may be the only demand side market.
By summarizing the factors that affect signal integrity, to better ensure signal integrity in the PCB design process, you can consider the following aspects.
(1) Considerations in circuit design. Including controlling the number of simultaneous switching outputs and controlling the maximum edge rate (dI / dt and dV / dt) of each unit to obtain the lowest and acceptable edge rate; Selecting differential signals for high-output function blocks (such as clock drivers); Terminate passive components (such as resistors, capacitors, etc.) to achieve impedance matching between the transmission line and the load.
(2) Minimize the trace length of parallel wiring.
(3) Place the components away from the I / O interconnect interface and other areas that are susceptible to interference and coupling, and try to reduce the placement interval between the components as much as possible.
(4) Shorten the distance between the signal trace and the reference plane.
(5) Reduce the trace impedance and signal drive level.
(6) Terminal matching. Termination matching circuits or matching components can be added.
(7) Avoid parallel wiring and routing, provide sufficient wiring space between the traces, and reduce inductive coupling.
