The rapid development of today's electronic design, high-speed and miniaturization has become a trend, how to reduce the volume of electronic systems, while maintaining and improving the speed and performance of the system designer before becoming an important issue. EDA technology has developed a set of high-speed PCB and board-level system design and analysis tools and methodologies, these technologies cover all aspects of high-speed circuit design and analysis: static timing analysis, signal integrity analysis, EMI / EMC design, ground bounce analysis , power analysis and high-speed router. It also includes signal integrity verification and Sign-Off, design space exploration, proposed interconnection plan, a comprehensive electrical interconnection rule-bound, and expert systems technology for efficient methods are also better solve signal integrity problems possible. Signal integrity problems will be discussed here in the method of analysis and control signal crosstalk.
Crosstalk signal generated by the mechanism
Crosstalk refers to a signal transmitted over a transmission channel, generated by the electromagnetic coupling of the undesirable effects of adjacent transmission line, the performance of the interference signal is coupled into a voltage and a current coupling. Excessive crosstalk may cause false triggering of the circuit, cause the system to not work properly. The circuit shown in Figure 1, the gate is called AB interference between the source network (Aggressor Line), the gate CD called interference between the source network (Victim Line). A change state as long as the source of interference, we can observe a pulse source of crosstalk at the victim.
Figure 1 crosstalk interference source network and network interference
Signals transmitted on the transmission channel of the transmission line adjacent to the noise caused by two different signals: a signal of capacitive coupling and inductive coupling signal, Figure 2, Figure 3. Since the capacitive coupling of the electromagnetic interference voltage (Vs) source of interference (Aggressor) on the induced current caused by the change in the interference object (Victim) on (i) caused by the mutual capacitance Cm, which is due to the inductive coupling noise source field current (Is) generated by the change caused by the induced voltage (V) is the interference in the object by the mutual inductance (Lm) as a result of electromagnetic interference.
3 Schematic diagram inductive coupling
Several important features crosstalk analysis
Effects of current flow of crosstalk
Crosstalk is a direction, which is a function of the direction of current waveform, signal simulation we look at two cases here. The first case is the same current flows and the source of interference is the interference wire mesh wire mesh object, the second source of interference is that current flow is disturbed and the wire mesh of wire mesh object opposite (that is, the point B as the drive source, and A point of the load). AB and CD are added to the reticle 20MHz signal crosstalk in Table 1 shows the distal end of the peak at point D, crosstalk waveform simulation results shown in Figure 4.
Table 1 Current flow is not the same peak crosstalk
From the simulation results, the reverse current flow when the remote crosstalk peak (357.6mm) is far greater than the current flowing in the same direction when the port crosstalk peak of (260.5). And can be seen from Figure 4, when the current flows to the interference source changes, the polarity of the crosstalk interference source is also changed. This shows the magnitude and polarity of crosstalk and noise source corresponding to the signal current flows related.
(A) current in the same direction when the crosstalk waveform
(B) current waveform reverse crosstalk when
Figure 4 on the peak current flowing
Point D is generally greater than the distal end proximal end crosstalk crosstalk point C, thus suppressing crosstalk, the distal end crosstalk factor is usually the point D as the reticle inspection peak voltage magnitude of the crosstalk key consideration.
The frequency of the signal source and the edge flip rate
Interferer signal frequency, the greater the amplitude of the crosstalk interference on the object, when we signal frequency f1 in Figure 1 the source of interference on the network AB values were taken at different frequencies, crosstalk interference on the simulation objects, The simulation results are shown in Table 2, the signal is not the same frequency crosstalk waveform shown in Figure 5, labeled "1", "2" wave frequency are indicated by the arrows "500MHz", "100MHz".
Table 2 peak frequency crosstalk interference sources for different values of
The simulation results shows that the frequency of cross-talk and interference source signal voltage is proportional to the value of the interference object when a large source of interference frequency 100MHz, must take the necessary measures to suppress crosstalk. Meanwhile, it can be seen from Figure 5, when the source of interference waveform when the frequency to 500MHz large, crosstalk interference apparent object point C has a large proximal end of its distal end crosstalk point D, this time indicating that the capacitive inductive coupling and coupling over a major confounding factors, in this case not only handle far-end crosstalk, and require careful handling is often easy to overlook the near-end crosstalk.
In addition, we analyze the impact of crosstalk Another great factor, it is the edge of the flip rate of the signal in the digital circuit, in addition to have a greater impact on the frequency of the signal crosstalk, the edge of the flip-rate signal (rising and falling along) greater impact on crosstalk, edge change sooner, the greater crosstalk. Due to the design of modern high-speed digital circuits, with a larger edge flipping rate applications devices more widely, so for these devices, even if the signal frequency is not high, in the wiring should be taken seriously in order to prevent excessive The crosstalk.
(A) The object also end crosstalk interference waveform
(B) the remote object crosstalk interference waveform
Figure 5 is not the same crosstalk signal frequency waveform
(A) The object also end crosstalk interference waveform
(B) the remote object crosstalk interference waveform
Figure 6 crosstalk waveform P and two parallel line spacing for different values of length L
Line spacing P and the two lines parallel to the length of the impact of crosstalk size L
For a two-wire system of Figure 1, we conducted a simulation (the frequency of the signal line network are AB 100MHz) simulation results shown in Table 3, and 6, the three cases: The first case is the distance between two lines Under the same conditions and parallel length, object detection crosstalk interference (labeled "1"); second situation is parallel to the length of the two lines in the same premise, the two line spacing to 10mils, then probe interference Crosstalk Mark object "2"; The third case is a two-wire spacing in the same conditions, the two lines will be parallel to the length of 2.6inches labeled "3", and then detect the crosstalk interference objects. Seen from the simulation results when the distance between the two lines of the widening (P into the 5mils 10mils), the crosstalk is significantly reduced, and when two parallel lines extending the length (L into the 1.3inches 2.6inches), crosstalk significantly increased.
It can be seen, the size and spacing of the crosstalk is inversely proportional to the voltage of the two lines, and proportional to the length of two parallel lines, but not entirely multiple relationships. When the wiring space is small or large wiring density, high speed circuits in the actual wiring, in order to prevent the high-frequency signal line adjacent to the signal line may cause crosstalk false triggering gate, allowing the routing resources in under conditions likely to be opened near the line spacing (except differential line) and reduce the length of two or more parallel signal lines, can be used to push a fixed maximum length parallel wiring if necessary (also known jog style traces ), so we can save tension routing resources, and can effectively suppress crosstalk traces schematic shown in Figure 7.
Figure 7 jog style traces
Table 3 two-wire crosstalk peak P and parallel to the length of the pitch for different values of L 
Horizon facing the influence of crosstalk
Multilayer PCB board typically includes a plurality of signal layers and a plurality of power supply layer, a plurality of signal and power planes are constituted by sequentially stacking a standard microstrip and stripline transmission lines. Microstrip transmission line and the strip line between adjacent power plane generally has a corresponding signal layer and power layer is a dielectric filled. The thickness of the important factors affecting the dielectric layer of the characteristic impedance of the transmission line when it is thicker, the characteristic impedance of the transmission line becomes large when it is thin, the characteristic impedance of the transmission line becomes small.
Great influence of the thickness between the transmission line and the ground plane of the dielectric layer crosstalk, for the same wiring structure, when the thickness of the dielectric layer is doubled, significantly increased crosstalk. Meanwhile, for the same thickness of the dielectric layer, the strip line is a microstrip transmission line is smaller than the crosstalk crosstalk seen, transmission line effects of amlodipine face different structures are different. Therefore, when the high-speed PCB layout, use stripline better than using microstrip transmission crosstalk suppression.
Crosstalk control
To eliminate cross-talk is not possible, we can control the crosstalk in the tolerable range. So we can take the PCB design during the following approach:
① If the wiring space allows, increase the spacing between the lines of; When ② meter stack, to meet the requirements of the impedance conditions, reduce the height between the signal layer and formation; ③ critical to design high-speed signal into a differential line right, such as the high-speed system clock; ④ If the two signal layers are adjacent, wiring wiring orthogonal direction to reduce the coupling between the layers; ⑤ into the design of high-speed signal lines embedded stripline or microstrip line; When ⑥ alignment, reducing the length of the parallel lines, can jog mode wiring; ⑦ In the case of the system design to meet the requirements to make use of low-speed devices.
