Ground plane
In fact, far more than the content needs to be discussed in this article mentioned this, but we will focus on highlighting some of the key features and encourages readers to further explore this issue.
Common ground plane to play the role of a reference voltage, to provide shielding, heat dissipation can be reduced and the parasitic inductance (but it also increases the parasitic capacitance) functions. Although there are many benefits to using a ground plane, but in the realization must be careful because it can do and has some limitations can not be done.
Ideally, PCB with a ground plane layer should be specifically used. So that when the entire plane is not destroyed will produce the best results. Do not misappropriate this dedicated area ground plane layer for connecting other signals. Since the magnetic field can be eliminated between the ground plane conductor and the ground plane, a printed wiring inductance can be reduced. If a damaged area of the ground plane, the ground plane will printed above or below the line into unexpected parasitic inductance.
Because the ground plane generally has a large surface and cross-section, so that the resistance of the ground plane kept to a minimum. At low frequencies, the current will choose the path of least resistance, but at high frequencies, the current will choose the path of least resistance.
However, there are exceptions, and sometimes a small ground plane will be better. If the ground plane from the input or output pad next move away, high-speed op amp will work better. Because the ground plane at the input parasitic capacitance is introduced to increase the operational amplifier's input capacitance, the phase margin is reduced, resulting in instability. As discussed in the section parasitics see, op amp input capacitance of 1 pF can cause obvious spikes. The output of the capacitive load - including parasitic capacitive loads - resulting in a feedback loop poles. This will reduce the phase margin and cause the circuit to become unstable.
If possible, analog circuits and digital circuits - including their own ground and the ground plane - should be separated. Fast rising glitch will cause the current flowing into the ground plane. The noise caused by the rapid current spikes will destroy the analog performance. Analog and digital ground (and power) should be connected to a common ground to reduce the circulating current, and digital and analog ground noise.
In the high frequency must be considered called "skin effect" phenomenon. The skin effect causes current flow to the outer surface of the wire - the wire cross-section so that the result will be narrowed, so that current (DC) resistance increases. Although skin effect is beyond the scope of this article, here is given in the copper skin depth (Skin Depth) is a good approximation formula (in cm):
Low sensitivity of the plated metal helps to reduce skin effect.
Package
Operational amplifiers typically use different packages. The selected package will affect the frequency performance of the amplifier. The main effects include parasitic effects and signal paths (previously mentioned). Here we focus on the path to the amplifier input, output and power supply.
Cabling Figure 9 shows the difference in SOIC package (a) and SOT-23 package (b) between the op amp. Each package has some problems of its own. Emphasis see (a), carefully observe the feedback path found a variety of ways to connect feedback. The most important is to ensure that the minimum length of the printed lines. Feedback path parasitic inductance will cause ringing and overshoot. In Figure 9 (a) and 9 (b), the feedback path around the amplifier is connected. Figure 9 (c) shows another way - to connect the feedback path in SOIC package below - thus reducing the length of the feedback path. Each method has its nuances. The first method will lead to the printed line is too long, to increase the series inductance. The second method uses a through-hole, causing parasitic capacitance and inductance. When wiring to the PCB must consider the impact of these parasitic effects and the potential problem. SOT-23 wiring difference is almost ideal: the length of the shortest feedback traces, and rarely use through-hole; loads and bypass capacitors from a short path to return to the same ground connection; positive supply side of the capacitor (Figure 9 (b) not shown) directly below the back of the negative power supply PCB capacitor.
Low distortion amplifier pinout: ADI offers some of the operational amplifier (eg AD80451) introduced a new low-distortion pinout, helping to eliminate the two problems mentioned above; but it also improves the other two an important aspect of performance. LFCSP low distortion pinout shown in Figure 10, the traditional op amp pinout according counterclockwise to move a pin and added an output pin as a dedicated feedback pin.
Low distortion pinout allows the output pin (dedicated feedback pin) between the inverting input pin and can close the connection shown in Figure 11. This greatly simplifies and improves the wiring.
Another advantage of this pin arrangement is to reduce the second harmonic distortion. Traditional op amp pin configuration second harmonic distortion caused one of the reasons is the non-inverting input coupling between the pin and the negative supply. LFCSP with low distortion pinout eliminates this coupling it greatly reduces second harmonic distortion; in some cases can be reduced up to 14 dB. Figure 12 shows the difference AD80992 SOIC package and LFCSP packages distortion performance. 
This package has another advantage - low power consumption. LFCSP package has an exposed pad, which reduces the thermal resistance of the package, which can improve the θJA value of about 40%. Because reducing the thermal resistance, so reducing the operating temperature of the device, it is equivalent to improve reliability.
Currently, ADI offers new low-distortion pinout three speed op amps: AD8045, AD8099 and AD80003.
Wiring and shielding
A variety of analog and digital signals, including high to low voltage or current is present on the PCB, from DC to the GHz frequency range. Ensure that these signals do not interfere with each other is very difficult.
Recall "Do not believe anyone" part of the proposal, the most critical is the pre-order thinking and how to handle signals on the PCB to work out a plan. What is important to note that the signal is sensitive to signals and determine what measures must be taken to ensure the integrity of the signal. Providing a ground plane for the common electrical reference point and to be used for shielding. If you need to signal isolation, first of all should stay out of the physical distance between the signal traces. Here are some practical experience is worth learning:
* Close to the same degree of reduction of long parallel PCB and the signal line length between the printed lines can be reduced inductive coupling.
* Reduce the length of the adjacent layers of the printed length to prevent capacitive coupling.
* Requires high isolation signal traces should take a different layer and - if they are not completely isolated words - should take the orthogonal traces and the ground plane is placed between them. Orthogonal lines can minimize capacitive coupling, and form an electrical ground shield. When composing controlled impedance traces can use this method.
High-frequency (RF) signals typically in the control flow line impedance printing. That is, the printed lines to maintain a characteristic impedance, such as 50 Ω (RF applications typ). The two most common printed controlled impedance line, a microstrip line 4 and strip line 5 can achieve a similar effect, but of different methods.
Printed controlled impedance microstrip line shown in Figure 13 can be used on any side of the PCB; directly used as the ground plane below the reference plane.
Equation (6) can be used to calculate the characteristic impedance of an FR4 board.
H denotes the distance from the ground plane to the signal traces between, W represents the width of the printed lines, T represents the thickness of the printed line; All dimensions are in mils (mils) (10-3 inches) units. er a dielectric constant of PCB material.
Printed controlled impedance strip line (see Figure 14) using a ground plane layers, in which the clamp signal produced. This method uses a more traces, PCB layers required more sensitive to changes in the thickness of the dielectric, and higher costs - it is usually only used for demanding applications.
The characteristic impedance of the strip line for the calculation shown in Equation (7) below.
Protection ring, or "isolation ring", the operational amplifier is used to mask another method for preventing the current flowing into the parasitic sensitive node. The basic principle is simple - sensitive protective conductor with a junction that is fully enclosed, or forcing it to keep holding the wire (low-impedance) sensitive junction with the same potential, and therefore the absorption of the parasitic currents away from the sensitive nodes. Figure 15 (a) shows an inverting op amp configuration and schematic phase configuration with the guard ring. Figure 15 (b) shows a typical wiring method of SOT-23-5 in two packages for protecting ring.
Epilogue
PCB layout for a high level of success of the operational amplifier circuit design is very important, especially for high speed circuits. A good principle is the foundation of good wiring diagram; close coordination between circuit design engineers and layout designers is fundamental, especially questions about the position of the device and wiring. Issues to consider include bypass power, reducing the parasitic effects, the use of the ground plane, the impact of operational amplifier package, as well as wiring and shielding.
