Challenges of high speed and high density PCB design, designers need to change not only tools, as well as designed, concepts and processes.
With the improvement of the increasing complexity of electronic product features and performance, the frequency-density printed circuit boards and their related devices are rising, the challenges facing engineers designing high-speed high-density PCB brought increasing. In addition to well-known signal integrity (SI) problems, senior manager of Cadence's high-speed system technology center Chen Lanbing believe that the next hot technology should be a high-speed PCB power integrity (PI), EMC / EMI, and thermal analysis.
With increasing competition, time to market pressures facing manufacturers is also growing, how to use EDA tools and advanced optimization methods and processes, high-quality, high efficiency to complete the design, system vendors and has become Design engineers have to face the problem.
Hot: Transfer from signal integrity to power integrity
Comes to high-speed design, people first thought is that the signal integrity issues. The main signal is the signal integrity in the quality of the signal transmission line, when the timing, duration and magnitude of the voltage signals in the circuit can be required to reach the receiver chip the pin, the circuit has a good signal integrity. When the signal or the signal quality not normally respond to long-term stability can not make the system work, it appeared signal integrity problems, signal integrity delayed mainly manifested in several ways, reflections, crosstalk, timing, oscillation. Generally, when the system is operating in 50MHz, will produce signal integrity problems, and with the frequency of the system and the device continues to rise, signal integrity issues will become more prominent. Parameters of components and PCB board layout components in these problems, such as high-speed signal routing the PCB can cause signal integrity problems, leading to system instability or even completely does not work.
Signal Integrity technology after decades of development, the theory and methods of analysis have been more mature. For signal integrity problems, Chen Lanbing believe, signal integrity is not a personal problem, it involves every aspect of the design chain, not only the system design engineers, hardware engineers, PCB engineers to consider, even at the time of manufacture can not be ignored. Solve signal integrity issues, must use advanced simulation tools, such as Cadence's SPECCTRAQuest is a good simulation tool, which allows you to modeling, simulation early in the design to form bound by the rules guiding the late layout, improve design efficiency. With Cadence launched in June this year, specifically for gigahertz signal simulator MGH - it is the industry's first to be completed tens of gigahertz signal BIT emulator within a few seconds - Signal Integrity technology perfected .
Relative to the signal integrity, power integrity is a relatively new technology, it is considered one of the high-speed high-density PCB design biggest challenge. Power Integrity refers to the high-speed system, the power transmission system (PDS power deliver system) on different frequencies, different impedance characteristics, the voltage between the power supply layer and formation throughout the PCB board is different, resulting in a continuous supply does not generate power supply noise, the chip does not work; same time as the high-frequency radiation, power integrity issues will bring EMC / EMI problems. If you can not solve the problem of power integrity, will seriously affect the normal operation of the system.
Typically, power integrity problems are mainly two ways to solve: optimizing circuit board design and layout of the stack, as well as increased decoupling capacitors. When decoupling capacitors in the system frequency is less than 300 ~ 400MHz, can play suppress frequency, filtering and impedance control role, the right place at the right position decoupling capacitors help to reduce system power integrity problems. But when higher system frequency, decoupling capacitors little effect. In this case, only by optimizing the spacing of the circuit board layer and the layout design, or other reduced power, ground noise methods (as appropriate to match the power transmission system to reduce the problem of reflection) and the like to solve the problem of the integrity of the power supply while suppressing EMC / EMI.
The relationship between the signal and power integrity, and Chen Lanbing that: "Signal integrity is a conceptual time domain, better understanding, and it is a frequency domain power integrity concept difficult than the signal integrity, but there are certain aspects and signal integrity in common. power integrity engineers require higher skills, for high-speed designs, is a new challenge, which is not only related to the board level, involving both the chip and package level recommended in high-speed circuit board design engineers to do to solve the power integrity on the basis of the signal integrity. "According to reports, Cadence has the power integrity tools PI market, and has been successfully applied to many customers in the design .
Through simulation, "soft" of your design
The simulation is put into consideration all aspects of virtual prototype testing. Due to increasingly complex designs, engineers impossible to implement each program are used, only this time instead of using advanced simulation test to judge.
System design today, in addition to facing the challenges of high-speed high-density circuit boards brought outside, the pressure is more rapid product launch is to make the simulation system designed to become an essential tool. The designer wants to use advanced simulation tools to identify problems in the design stage, so efficient, high quality complete system design.
Traditional circuit board design, simulation tools help engineers rarely. More often is the use of reference designs and design rules to guide the upstream chip vendors (ie, white papers), combined with practical experience of engineers to design and prototype design produced repeated test trials, identify problems, modify the design, This cycle, until the problem is basically resolved. Instant occasionally using simulation tools to design, it is only a partial circuit. Modify time delay circuit means, and this delay in product launch rapid pressure is unacceptable, especially for large systems, a small change may need to be reversed to the entire design, are so-called "trigger off as a whole, "the loss caused to the manufacturer it is immeasurable.
Difficult to guarantee the quality of products, the development cycle of uncontrollable, excessive reliance on engineers experienced ...... These factors make it difficult to deal with the above design increasingly complex challenges of high-density, high-speed PCB design brings, therefore must use advanced simulation tools to solve them. "Upstream chip manufacturers for the design is based on their own template, and the product model and the upstream vendor system vendors can not be completely the same; while a chip design and other requirements may be contradictory, and this When the design must be determined by simulation. "陈兰兵 said.
In a sense, the simulation is to let the software needed to complete the functional assessment before physical prototypes through to be able to complete the test in a virtual prototype, is a more "soft" technology and a more economical solution.
However, high-speed simulation and emulation of traditional high-density circuit boards are different. Mentor Graphics Corporation engineers You Lifu description: "The traditional simulation is done for the schematic, it's just added incentive to see the output, thereby to determine the function correctly; while the high-speed simulation is in the correct function of the premise, see Design How performance, both for the schematic for the same PCB design. "using the simulation tool to determine which solution closer to the actual demand, to meet the performance requirements on the basis of which a judgment of a lower cost design and performance find a balance between system cost. said: "The use of simulation tools, the system can determine the correct direction of improvement, indicating the direction for the design and improve the success rate of a board, make products faster to market, however, no matter how close the results of the simulation results of the test, it can not. instead of the actual test system. "
Testing is a reality that contains all environmental factors to determine system performance as a real, but it is a virtual prototype simulation "test", is for a particular condition, no one tool can take into account all the conditions are all at the same time realistic emulation. However, as technology continues to improve development and tools, simulation results and the approximation of the actual test results increasingly high significance for guiding the design is also growing, but engineers also put forward higher requirements - - While more and more tools to use, but the judgment of the simulation results and improved methods rely on technical and theoretical foundation engineers.
Currently in high-speed PCB simulation, the effect is most unsatisfactory EMC / EMI. This is because the high-speed system, because of the effect of through-hole, the need for three-dimensional modeling system to effectively simulate the real environment. However, for PCB such a large and complex system, its three-dimensional modeling is very difficult. According , currently the main way of expert examination, both in accordance with internationally accepted standards will transform EMC / EMI problems to the PCB layout rules. Cadence's EMControl is such a similar rule checker expert system, while also providing a customized interface to facilitate customers to prepare for the company's EMC / EMI inspection rules. Mentor Graphics' Quiet Expert can check the EMI problems caused incorrect wiring structure, identify problems, and gives EMI causes and recommended solutions to problems.
Efficiency choice: automatic routing and parallel design
Schematic design of the circuit is more than "trace" go, there are many other requirements, schematic design tool should be able to link these requirements to the next support automatic routing, functional simulation and so on.
In order to find a richer efficient design path to solve time to market pressure, the product to market quickly, automatic routing and parallel design techniques have emerged.
"If you can make good use of automatic routing technology can reduce Sketchpad time, will be designed to improve the efficiency of PCB more than doubled." Chen Lanbing introduction. However, in order to achieve automatic routing, must use electrified Rules Manager, the system hardware design engineers, design engineers and design requirements of the circuit is passed to the PCB engineer.
For early relatively simple systems, the usual practice is hardware engineers to design requirements of a handwritten down, telling PCB design engineers how to do it. However, for complex systems, in the face of thousands of connections, numerous requirements, hardware engineers can not record each of these rules, PCB design engineers will not be able to check a bar and implementation. At this point, we need electrification rules manager will manage a variety of design requirements, hardware engineers and PCB design engineers can work on the basis of the same rules manager on. Cadence's Rules Manager Constrain Management (referred to as CM) has been seamlessly integrated into their design tools schematic and PCB design tools, hardware engineers, after the completion of the schematic design, the design requirements (electrical properties, DFT, DFM rules etc.) was CM automatically to the next link, automatic routing system according to these rules. Therefore, automatic routing is based on constraint-driven automatic routing rules based on, but must have a good understanding and be able to complete these constraints rules router, Cadence's Specctra can achieve both good unity.
For automatic routing technology, Chen Lanbing suggested, "If a company does not have a good technique, signal integrity problems can not be solved, it is recommended not to use auto-routing, because if not well-defined rules, the driver will not automatically correct wiring." Whether How well-developed tool, the computer can not completely replace the human brain behavior, and therefore it is impossible to have a 100% automatic routing. Earlier we mentioned the automatic routing is actually an interactive automatic routing, requires the participation of people: automatic routing rules also require some manual before further identified; require engineers to verify and modify after automatic routing is completed.
For conventional, relatively low-speed system design, many engineers may have had this experience with the Cadence OrCAD schematic drawing, and then do PowerPCB Mentor's layout. However, Chen Lanbing believe that this approach is no longer suitable in high speed design. "Data can not achieve complete conversion between different vendors' tools, such as: the traditional method of reading netlist impossible to some of the electrical schematic to the PCB design attributes and requirements, and thus not suitable for high-speed designs."
In addition to automatic routing for large-scale systems, parallel design is an effective way to improve the design efficiency. Parallel design that collaborative design is split into several parts of a circuit board, designed by the same few people. According , currently Mentor Graphics design tools in parallel can already do, if the design of a machine on the save, another machine can be seen immediately, and both sides of the connection can be automatically connected together, so can reduce the integration between different design tasks. said: "until later this year, Mentor Graphics company fully dynamic parallel design tool extremePCB can market to time, engineers can fully networked real-time parallel design like playing CS like that each design can be seen each other in real time, so you can easily cooperation between engineers in different places
. "For the parallel design, Chen Lanbing believe that it not only requires good design tools, methods need good design, he suggested, parallel design not of too thin, too wide, 2 to 3 more reasonable, otherwise the idea is too scattered, but is not conducive to the design is reported, Cadence's design tools will also be introduced in parallel in the next version.
Beyond PCB: high-speed system-level issues to consider
When the system is developed from a few megabytes to tens of Kyrgyzstan, chip design, packaging design, system design has been impossible to be considered separately. For high-end products in the design of the chip, you should consider packaging design and system design.
After removal of the software itself, how to streamline processes, reduce errors from the process engineers, enabling engineers to put more energy into designs make our products enter the market as soon as possible, has become the content EDA vendors are considered.
Typically, the connecting wire on one system starts chip (Silicon) The I / O, encapsulated (Package) The bump and substrate, the package reaches the pin, then through the PCB, to another package pin, substrate, bump, and chip I / O. Chip, package, board, these are the three different areas, before considering the engineers will not go in the design, there is no way to know the idea of other engineers. But with the improvement of the design frequency, the chip area is reduced, shortening the design cycle, manufacturers are doing should be considered when designing the chip to the package design and PCB design, so effectively combine the three. Chen Lanbing that "this time in terms of signal integrity, that was from the design cycle, we should also consider Silicon-Package-Board design, and coordinate with each other links between them. Example, sometimes in the PCB Timing will be difficult to solve the problem, but in a Package can be easily resolved. "
As an active advocate of Cadence system-level design flow, the Allegro platform that covers the board-level design and package-level design, and a few other chips can be cascaded together Cadence Design Platform, a complete design chain, data is valid exchange and communication. In addition, Cadence's VSIC (Virtual System InterConnect) design approach is a new Silicon-Package-Board co-design method, which allows engineers early in the design can consider the issue of the timing or signal integrity throughout the system caused solved gigahertz signal design is a major bottleneck.
Allegro DesignWorkbench is the first electronic design and MatrixOne PLM jointly launched (Product Lifecycle Management) product, to ensure that the engineers at the right time, the right place, to select the most appropriate device. "It will certainly be an existing design flow far-reaching consequences, may shorten design cycles by 50% engineers," said Chen Lanbing.
