label: PCB layout,printed circuit board,PCB design
In this product-how to, ANSYS’ Steve Pytel explains how to use the ANSYS SIwave-DC simulation tool to predict DC power loss and voltage drop for a PCB.
As supply voltages continue to decrease and transistor count follows Moore’s law, power delivery network (PDN) integrity has become an important consideration for any electronic package or PCB design. Prediction of the PDN performance is critical to ensure consumer electronic products function as specified and meet battery life expectations.
It is often necessary to predict the DC performance of power rails to ensure that enough via transitions exist and adequate copper weighting (½ oz, 1 oz, 2oz, etc.) is present to minimize voltage drops during turn-on events and normal operation. Using the ANSYS SIwave-DC simulation tool, we can predict DC power loss and voltage drop for a PCB and then use those results to improve the PCB layout prior to fabrication.
For example, in the design in Figure 1, the Vcc power rail supplies 1.8 VDC power to two CPUs (U1 and U2). The initial layout brings power from the voltage regulator module (VRM) through an inductor to each of the CPUs. Vcc has only one via transition from layer 1 to layer 5. This results in 8.3 amps through the single via, causing the farthest CPU (U1) to see a 150 mV (~8%) voltage drop. In addition, layer 1 dissipates ~1.2 watts of power which must be reduced to meet the supplied specification.
The improved design shown in Figure 1 added a ½ oz. copper flood on layer 1 along with an additional 10 via transitions from layer 1 to layer 5. This improved design shows a better current distribution resulting in less voltage drop at the farthest CPU (U1). Another significant advantage is the power dissipated on layer 1 was almost cut in half due to the addition of the copper flood in the improved design. The original power dissipated due to joule heating within the PCB was ~1.2 Watts but, due to the simple design change, the power dissipated was reduced to ~0.6 Watts. In addition to the power loss, voltage drop and current vector results, the path resistance between sources and sinks was calculated. For the initial design the path resistance from the VRM to U1 was 18.3 mW, and for the improved design it dropped to 9.093 mW.
Using simulation to identify potential power integrity problems such as DC voltage drop and excessive current density is essential for today’s high-speed digital designs. With a powerful simulation package, it is possible to perform pre-layout PDN analysis and reduce post–layout power delivery problems.
