Do you design or define PCB layouts? If so, what rules and checks do you have in place to make sure your results are... optimal?
Over the years, I've created a PCB design checklist to keep me out of trouble. I share these nuggets with my layout person as required. Allow me to share some with you.
Starting out
The first thing I always say is "Do not let the tools dictate the board. Imagine how the board should be, then implement it. If it's too difficult, consider new tools. But still implement it." I think that's self-explanatory.
Planning is the critical first step. Plan a stackup. Plan the part placement. I'm sure you can chime in with more.
In my book, stackup is almost an art. There are so many dimensions to consider, and some always conflict. Reduce cost by minimizing layers, but don't go so far that it takes an extra month to lay out the board, SI suffers, or you just can't fit all those parts into the space allotted. You usually want to keep the layout balanced around the center of the stack. This minimizes warpage, which is a really bad thing when you have large SMT components.
Try to have your board fab team selected before you start. They can answer general and DFM-related questions and help you get your controlled-impedance traces right. The fab will almost always make slight adjustments to your controlled-impedance traces to compensate for their processes. The tighter your design is, the more you'll have to concern yourself with this.
Make sure all special requirements are spelled out, whether in documentation or as part of the schematic. These can be things like high-current nets, thermal sinks, length matching, controlled impedance... but I'm getting ahead of myself. We'll get to some of those in the high-speed area. Sometimes you can draw a schematic to hint at the required layout. A classic example is a single-point ground node. Of course, this only works if your board designer knows to look at the schematic and can understand your notations!
On any design that's even approaching high-speed, I always insist on a good density of ground vias sprinkled throughout the board, so that a good scope-probe ground is always available, no matter where you're probing. These should be circled on both sides for easy identification. Hell, they should glow in the dark.
I'm a great fan of flooding – on lower-speed double-sided boards, at least. Flooding unused areas with ground (and power sometimes) is a great way to improve power quality. It can improve etch consistency and reduce coupling, and it is a good idea environmentally – there's that much less copper to be eaten away.
A similar concept is thieving, which is often used on higher-speed multilayer boards. Here, empty areas are filled, not with a solid flood, but with a pattern of dots, a grid, or something similar. This helps maintain an even copper density over the layer, which again helps with warpage. Given the concerns I've read about floating islands on high-speed boards (leading to coupling or a resonant patch), dots are probably better than grids.
High speed
Once again, planning plays a critical role. Where will all your critical nets live in the stackup? What impedances are required? Do I have enough layers to route them all cleanly?
I'm sure everyone knows never to cross a plane gap with a high-speed signal. But consider this situation. A trace runs between a ground plane and a power plane. However, the power plane is cut up – it handles several different voltages. What do you do?
When I first ran into this, I intuitively felt that, if the ground plane was significantly closer to the signal layer than the power plane, you could cross power gaps without much of a problem. I played with a stackup editor to see how far the power plane would have to be to stop having much effect on trace impedance. Sure enough, this provided good SI. I later read an article by SI guru Eric Bogatin that covered this exact situation. He said the split plane should be at least four times farther from the signal than the reference plane.
"Impedance coupons" (test traces) should always be requested from the board shop. This way, there's never any doubt that your boards are within spec. And definitely enlist the shop's guidance if you have multiple impedances on your PCB.
Avoid vias as much as possible, though there are ways to impedance-match vias to the trace. Make sure your layout tool places pads only on the required layers, and consider blind/buried vias. If a signal changes reference planes when passing through a via, add an adjacent ground via. If one of the reference planes is power, decouple the power at that point.
High-speed nuggets
•Consider via-in-pad. Though this adds cost, total cost may be reduced if you can eliminate a couple of layers.
•Remove planes (and traces) as required – on edge connectors, for example, or under pads and components that need minimal capacitance.
•Consider power/ground plane pairs placed as closely as your board shop can manufacture. This provides great distributed high-frequency decoupling capacitance.
•This may be extreme, but I keep silkscreen legend off very high-speed traces. And make sure production won't stick labels there!
•I bury clock traces whenever possible. This provides a significant EMI improvement over microstrip. If you can't, surrounding the clock trace with well grounded shield traces may have a similar effect. Remember to compensate for the impedance change.
•Route with curves, not angles.
•Minimize power inductance by placing power layers closest to the side where the most critical components using that voltage are.
•For the same reason, I usually place ground layers at L2 and L(n-1).
•Ground planes should extend beyond the power plane and trace area to maintain proper impedances and reduce emissions.
•Add ground stitching vias wherever the natural via density is low.
