Keyword: pcb board, PCB, PCB package design, PCB package system
eASIC and Computer Simulation pcb board Technology (CST) have teamed up to significantly reduce multi-level PCB package design and simulation. The solution will be presented at the pcb board Industry Spotlight session at EPEPS 2013 (Electrical Performance of Electronic Packaging and Systems) on October 28th.pcb board The solution focuses on PCB package co-design and provides accurate pcb board, effective decomposition and segmentation modeling techniques for PCB package systems co-simulation.
The techniques allow accurate accounting pcb board of all discontinuities present at the package interface while saving significant computational effort and resources. The methodologies reduce co-simulation time by up to 5X when compared to the full model simulation pcb board, while preserving higher accuracy when compared to traditional partitioning practices pcb board.
