High-speed systems, noise interference is the first factor, the high-frequency circuit will produce radiation and conflict , while faster edge rates are ringing , reflection, and crosstalk. If you do not consider the special nature of the high-speed signal layout and design of the circuit board will not work properly . So successful is the PCB board design DSPs circuit design process is very critical aspect .
A transmission line effects
1.1 Signal Integrity
There reflection signal integrity , ringing, ground bounce and crosstalk phenomenon. The PCB traces can be equivalent to a series and parallel as shown in Fig capacitance, resistance and inductance structure. Typical values for the series resistance 0.25D./R-4). 55DJft, parallel resistance is usually high . After the parasitic resistance , capacitance and inductance added to the actual connection of the PCB , the final connection is called a characteristic impedance of the impedance zo.
If the impedance of the transmission line and the receiver do not match , this will cause signal reflections and ringing .
The geometry of the wiring , incorrect wire termination factors after discontinuous variation of the connector of the power transmission and reflection planes will result . Overshoot and undershoot are signal changes level rising and falling electricity generated will produce higher or lower than the steady level of glitches in an instant , easy to damage the device . Ringing and oscillation signals are respectively surrounded by the line inductance and capacitance inappropriate should played . Ringing can be reduced by proper termination.
When the circuit has to play the lead when a large current surge, if a large transient currents in the plane of the chip and the board 's power flows through the parasitic inductance and resistance of chip packaging and power planes will lead to power supply noise . Crosstalk is the coupling problem between two signal lines , the mutual inductance between the signal line and the mutual capacitance leads to a noise line. Coupled currents caused by capacitive coupling , and inductive coupling caused by the coupling voltage. Parameters PCB board layers , the signal line spacing, crosstalk has a certain impact driver and receiver electrical characteristics and wire termination methods .
1.2 Solution
To solve the common problem of some measures need to be taken :
Power planes for the current direction is not limited to the return line and the signal line that is closest to walk along the path of least impedance . This may make the smallest current loop , and this will be the preferred method of high-speed system . But do not rule out the power line noise level , pay attention to the power distribution paths , all systems will generate noise that caused the error . Requiring special filter is implemented by a bypass capacitor. L shrimp to lOp.F generally a capacitor on -board power input, and 0.01pF to U0.1 heart capacitance on the board between the power of each active devices , ground pin . Role as the bypass capacitor filters, large capacitor (10aF) on the low-frequency (60Hz) power input , filter plates outside noise generated on-board noise generated by the active devices in the 100MHz or higher frequencies produce harmonics, placed between each chip bypass capacitor is usually higher than on -board power input capacitance is much smaller.
According to experience , if the design of mixed analog-digital , analog and the digital PCB partition portion , analog portion on the analog and digital devices on the digital part , A / D converter is placed cross . Analog and digital signals in the respective wiring region , ensure that the digital signal back to an analog current signal does not flow to the ground.
Bypassing and decoupling is to prevent the transfer of energy from one circuit to another circuit , power supply layer , the bottom line layer , components and internal power connector 3 circuit area needs attention. Try widening power , ground width , preferably ground than the power line width, their relationship is : Ground > Power cable> signal line , usually signal linewidth : O.2 ~ O.3mm, the smallest width up to 0.05 "-'' 0.07mm, the power cord is 1.2" -'' 2.5 n'' Lrfl. With a large area of ground used for the copper layer on the PCB is not the place to spend all connected with the land use as a ground . Or made of plywood , power , occupied the ground floor of each . Configure a heart 0.01 for each IC chip ceramic capacitors. In case of the small printed circuit board space and fit , every 4 to 10 may be configured with a l ~ 10 chips heart tantalum electrolytic capacitors, the high frequency impedance of such devices are very small, the impedance in the 20MHz range 500kI-Iz ~ less than lQ, and leakage current is very small (O.5LlA less ) . Decoupling filter capacitor must be close to the IC installation , and strive to lead the shortest and smallest capacitor transient current loop area , especially high frequency bypass capacitor can not take the lead .
For when the system is operating in 50MHz, will have integrity issues and signal transmission line effects , traditional measures can be taken to achieve satisfactory results ; whereas when the system clock reaches 120MHz, you need to consider the use of high-speed circuit design knowledge , otherwise based on traditional methods PCB design will not work . Thus , high-speed PCB circuit design has become the electronic system designers must master design techniques.
2 PCB high-speed signal circuit design techniques
2.1 high-speed signal routing
Both high-speed signal routing using multilayer wiring necessary , but also an effective means to reduce interference . To a reasonable choice to reduce the number of layers PCB size , full use of the intermediate layer shielding to set and achieve close to ground , can effectively reduce the parasitic inductance, shorten the length of the signal transmission , reducing cross-interference between signals , etc. , all of these high-speed circuits the reliability of the favorable work . Data shows that when 248 Eighth National Radiation Electromagnetic Pulse Electronics Symposium with the same kind of material , four double-sided boards , low noise than 20dB. Wire bending better, the best use of the whole line , you need to turn , can turn 45 degrees to a line or arc , can reduce emission and mutual coupling between the external high-speed signals , reducing the radiation and the reflected signal .
Lead -speed circuit between the device pins as short as possible . The longer lead , the greater the distributed inductance and distributed capacitance values brought , the system will lead to the occurrence of reflection high-speed circuit , oscillation . Speed circuit between the wiring layers are alternately between the device pins , the better is the element connecting vias used in the process , the better. According to measurements, a distribution of vias can bring about 0.5pF capacitor , resulting in a significant increase in the delay circuit . High-speed signal line wiring should be noted that the introduction of close parallel lines of " cross-talk " If you can not avoid parallel distribution can be arranged in a large area on the opposite side of the parallel signal lines "ground" to reduce interference. In two adjacent layers , be sure to check the alignment direction perpendicular to each other .
Measures of ground surrounded by a particularly important signal line or local unit implemented. These signals may be susceptible to interference such as clock signals , high-speed analog signals simultaneously traces the periphery of the protection ground with the signal to be protected in the middle of the clip . Various types of signal traces can not form a loop , can not form a ground loop currents . If a loop wiring circuit , will have a great disturbance in the system. * Daisy chain loops can effectively avoid the wiring cabling adoption. Should set a near each circuit block or a few high-frequency decoupling capacitors . Analog ground , digital ground , such as when connected to a common ground to use high-frequency choke link. Some high-speed signal lines should be special treatment : Differential signal requirements on the same level and close to flat as possible to walk the line , do not allow any signal is inserted between the differential signal lines, and requirements for long.
High-speed signal routing should avoid the formation of branched or tree stumps (Stub). Walking in the high-frequency signal lines prone to large surface electromagnetic radiation , the radiation frequency signal line wiring between the power supply and ground , through the power and the underlying absorption of electromagnetic waves generated will reduce a lot .
2.2 high-speed clock signal wiring
The clock circuit occupies an important position in digital circuits . C64xDSP is the newest member of the C6000 platform , it has a sufficiently high processing speed. C64xDSP high-speed clock can reach 1.1GHz, as early C62xDSP of lO times . So in the future application of modern electronic systems design DSP clock wiring requirements will be higher . High-speed clock signal line has the highest priority , generally in the wiring , you need to give priority to the master clock signal line system. High-speed clock signal line signal frequency is high , requiring traces as short as possible , to ensure minimal signal distortion .
High-frequency clock , are particularly sensitive to noise interference . The need for high-frequency clock signal line protection and shielding to minimize interference .
High-frequency clock (20MHz clock above , or rising less than 5ns clock ) must have a ground convoy , the linewidth of the clock at least 10rail, escorting ground linewidth at least 20mil. Protective earth at both ends of the high-frequency signal lines must be in good contact with the formation vias , and each hole 5em played around with the formation to be connected ; ground convoy line with the basic data , such as length , recommended hand- pull ; clock transmission side must string by one of about 22 ~ 220Q damping resistors. Design of high-speed clock signal traces on the same layer as possible designed around the high-speed clock signal lines are no other possible sources of interference and traces . High-frequency clock connection with a star connection or using point to point connection , using the T-connector to ensure equal arm length , minimizing the number of larvae L too , in crystal or clock chip need copper to prevent interference . Avoid signal noise caused by these lines produced .
When the high-speed signal routing and high-speed clock signal routing , require less travel time line played larvae L, small branches, stumps to avoid generating a signal reflections and crosstalk . Effect of vias and stakes (Stub) in the high-speed PCB reflected not only in the effect on the signal , but also lead to changes in the impedance of the wire . The impact of vias and stumps of impedance is often easy to overlook the problems designers .
To choose the right size of the hole size. For example, 4-layer PCB design layer 10 , the common choices for 10mil/20mil ( hole / pad ) , or preferably via 16mil/30mil , some small-sized high -density PCB, may also be used 8mil/18mil vias . To the power supply or ground vias can consider a larger size to reduce impedance. Power and ground pins to the nearest place vias , wire and pin through-hole between short as possible , while the power and ground leads to the largest possible to reduce impedance.
The latest high-density system-on- chip BGA or COB package, pin pitch is increasingly reduced. Ball pitch is low O.6mm, and will continue to reduce , leading packaged devices signal line wiring is not possible using traditional tools to lead . There are two ways to 249 Eighth National Radiation and Electromagnetic Pulse Electronics Symposium to solve this problem: ( 1 ) through the ball below the hole over the signal line drawn from the lower ; ( 2 ) the use of fine wiring and cabling to find a lead free angle channel ball grid array. BGA or COB packaging for such high-density devices , the use of minimal space and wiring width is the only feasible way , the only way to ensure a higher yield and reliability , to meet the requirements of high-speed design .
2.3 BGA package pad design
With the development of device packaging technology, packaging smaller relative size of the device . TMS320C6000 family of devices have up to 352 pins , because BGA pin pitch -intensive, too close to the hole from the pin , it will have a huge inductor. For high-speed signal is also harmful, so when BGA scattered holes , try using a smaller hole . There is a corresponding relationship between the foot pad size and pitch BGA BGA , but not greater than the diameter of the ball pin BGA , typically about its l/10 ~ l / 5. Vias BGA pad beside the pads on the component side required plug hole and covering green oil , for BGA soldering , surrounded by other devices can not appear within 2era.
3 Conclusion
Is the core digital signal processor for signal processing , and with the popularity of high-frequency devices , the printed circuit board density increases, the increased interference and improve the signal quality of the first mentioned design position . The high-speed DSPs of PCB board design is a very complex design process. There are several factors to be considered during high speed circuit design , each corresponding to these factors are . As the layout position near the high-speed device , can be reduced although the delay, but may produce significant heat and crosstalk effects ; possible when high-speed signal wiring traces and the inner hole is a little contradictory played . Therefore, in the design , needs to consider the various favorable factors, to make a comprehensive circuit design.
The only way to design anti-jamming ability , stable performance, real-time high quality PCB board .
