Vias (via) is an important component of a multilayer PCB , the cost of drilling PCB system board costs typically account for 30 % to 40 %. Simple to say, each hole on the PCB can be called vias.
From the point of view the role of vias can be divided into two categories :
One is used for electrical connections between layers ;
The second is used as a device fixed or positioning.
If the process from the process , these vias generally divided into three categories, namely blind hole (blind via), buried vias (buried via) and through-hole (through via).
Blind holes located on the top and bottom surface of the printed wiring board having a certain depth , for connecting the inner surface of the line and below the line , the depth of the hole is usually not more than a certain percentage ( pore diameter ) .
Buried in the connection hole is the inner bore of the printed circuit board , it does not extend to the surface of the board . These two types of holes are located in the inner layer circuit board , prior to lamination molding process is completed through a through -hole , the through hole forming process may also make several overlapping layer.
The third is called through-hole , this hole through the entire circuit board can be used to achieve internal interconnection or as an installation positioning hole components. Since the through hole in the process is easier to implement , low cost, so most of the printed circuit boards are to use it , rather than the other two through holes. Hereinafter called vias , no special instructions are considered as a through-hole .
From a design standpoint, a through-hole is mainly composed of two parts, one in the middle of the drill hole (drill hole), the second is drilling around the pad area , as shown below . Determines the size of the two parts of the through-hole size. Obviously, high-speed, high-density PCB design, designers always want vias as small as possible , so that the board can allow more wiring space , in addition, smaller vias its own parasitic capacitance also The smaller , more suitable for high-speed circuits. However, the pore size decreases , while the increased costs brought , and the size of the through-hole is reduced can not be unlimited , it is restricted drilling (drill) and the plating (plating) and other technology : the smaller the hole , the drill the longer it takes the hole , and also more likely to deviate from a central location ; and when the depth of the hole is more than six times the diameter of the drill hole , the hole wall can not be guaranteed even copper . For example, now a normal 6-layer PCB thickness ( through- hole depth ) is about 50Mil, so PCB manufacturers can provide a minimum hole diameter can reach 8Mil.
Two . Parasitic capacitance of the via hole exists own parasitic capacitance to ground , if it is known through the hole in the ground plane for the isolation of pore diameter D2, the diameter of the hole through the thickness of the pads D1, PCB board is T, the base plate the size of the parasitic capacitance of the dielectric constant material ε, the through-hole is similar : the main circuit will affect the parasitic capacitance C = 1.41εTD1 / (D2-D1) through the hole caused by the extended rise time of the signal , reducing the circuit speed.
For example, for a thickness of the PCB board 50Mil , if the inner diameter of 10Mil, 20Mil pad diameter of the through-hole from the copper pads and ground floor area is 32Mil, we can calculate the approximate equation at the through-hole parasitic capacitance is roughly:
C = 1.41x4.4x0.050x0.020 / (0.032-0.020) = 0.517pF,
This part of the rise time of the capacitance variation is caused by :
T10-90 = 2.2C (Z0 / 2) = 2.2x0.517x (55/2) = 31.28ps.
From these values , despite rising utility extension slows parasitic capacitance caused by a single through the hole is not very obvious, but if you take the line used repeatedly to switch vias between layers , designers still have to be carefully considered .
Three . Similarly via the parasitic inductance , parasitic capacitance via a parasitic inductance also in the design of high-speed digital circuits , the parasitic inductance of vias harm is often greater than the influence of parasitic capacitance. It would undermine the contribution of the parasitic series inductance bypass capacitor , weaken the effectiveness of the entire power system filter . We can simply use the following formula to calculate an approximate via parasitic inductance:
L = 5.08h [ln (4h / d) +1]
Wherein L represents the inductance through the hole , h is the length of the hole , d is the diameter of the central bore .
As can be seen from the formula, the smaller diameter vias affect the inductor , and the inductor had the greatest impact is the length of the hole .
Still using the above example can be calculated via an inductance of :
L = 5.08x0.050 [ln (4x0.050/0.010) +1] = 1.015nH.
If the signal rise time is 1ns, then the equivalent impedance size : XL = πL/T10-90 = 3.19Ω. Such impedance at high-frequency current can not be ignored by already , with particular attention to the bypass capacitor connected in time of need power and ground planes through two vias, the parasitic inductance such vias will increase exponentially .
Four . Via high-speed PCB design in the face of over- analyzing hole through the parasitic characteristics , we can see that in the high-speed PCB design, often seemingly simple vias will bring great negative effect to the design of the circuit. In order to reduce the adverse effects of parasitics hole had brought , as far as possible in the design can :
1 . Cost and signal quality from two considerations , choose a reasonable size of the hole size. For example, the memory module 6-10 layer PCB design , the choice of 10/20Mil ( drilling / pad ) vias better , for some small- sized high-density board , you can also try using 8/18Mil too holes. Under current technology , and more difficult to use the smaller size of the hole . For the power supply or ground vias can consider using a larger size to reduce impedance.
2 . Two formulas discussed above can be concluded that the use of thinner help reduce PCB board parasitics had two holes .
3 . Signal traces on the PCB layer does not change as much as possible , that is to say try not to use unnecessary vias.
4 . Power and ground pins to the nearest hole played the lead between vias and pins as short as possible , because they will lead to an increase in inductance . At the same time the power and ground leads as possible crude to reduce impedance.
5. In the vicinity of the hole to place the signal change over a number of ground vias layer nearest to the signal loop. You can even put some extra lot of ground vias on the PCB . Of course , the design also needed flexible. Through-hole model discussed above is the case each pad are also sometimes , we can reduce or even pad to remove some of the layers . Especially in the through-hole density is very large, may result in the formation of the copper layer laid down in a slot cut off the circuit to solve this problem in addition to the position over the hole , we can also consider the shop via the copper layer the pad size is reduced.
