When we think of a power distribution network (PDN), the first images that usually come to mind are FPGAs and CPUs. These circuits generally require ultra-low PDN impedance in order to maintain the appropriate voltage at the FPGA or CPU during the large dynamic current variations these devices present. This study focuses on a much smaller scale, addressing a very simple circuit that experiences related PDN issues. While the issues shown here may seem obvious to some, this is an excellent example of a very common problem.
A single tiny logic gate
The first case we’ll look at is a Fairchild NC7SZ04 ultra-high-speed inverter gate. This logic gate is a single inverter gate in an SOT-23 package, and it is part of a Picotest demonstration board designed to illustrate a PDN issue in a very simple low-power circuit (see Figure 1). The inverter gate is used as a buffer between a 10MHz clock and a 50 Ohm port. The output impedance of the logic gate is approximately 20Ω, and R20 adds an additional 30Ω Ohms to total 50Ω in order to match the coaxial cable and input terminator on the oscilloscope. Resistor R18 is a 0805 package film resistor, which was increased from 0.2 Ω (see Figure 2) to 1Ω in the tests here to make the device current signal easier to see, so the scaling is 1V/A. This resistor does contribute to the issue, but it is not the dominant term.
The very small section of the demonstration PCB that includes this logic gate is shown in Figure 2. The section shown is approximately 1.2” wide to provide some sense of scale. The decoupling capacitor for the logic gate, C14, is connected to the groundplane on the top side and three approximately 1/8” traces connect the capacitor to the 1 Ω resistor and to the Vcc pin of the logic gate.
The first thing that many will find surprising is that the edge speed of the logic gate is approximately 400ps (see Figure 3). This picture also shows the AC voltage across the decoupling capacitor using a 4GHz oscilloscope and a 4GHz active probe. The probe and scope combination have a rise time of approximately 125ps, so this measurement is not limited by the measurement bandwidth.
The peak-to-peak voltage at the decoupling capacitor is 89mV, which for a 5V part is not unreasonable. The voltage at the logic gate supply voltage pins is shown in Figure 4.
The peak-to-peak voltage at the logic gate has increased to more than 1V, which is far beyond the maximum recommended range for most 5V devices. This particular part has a very wide operating range of 1.65V-5.5V. With a nominal 5V input, this voltage still comes very close to the maximum operating voltage.
A 1.5GHz differential probe was used to measure the voltage across the 1Ω resistor and the frequency spectrum of the voltage. The measurement is shown in Figure 5
The very narrow current pulse and fast edge speed means that it is likely that the scope and probe combination are insufficient with the 1.5GHz differential probe. The same measurement is performed with a 20GHz oscilloscope paired with a 13GHz differential probe and the result is shown in Figure 6.
The peak-to-peak voltage is distributed between many elements, some resistive and some inductive. Since there is no groundplane under these traces, the expected inductance is estimated at 20nH/inch.
And this simple calculation is in very good agreement with the measured result in Figure 3.
Another impact of the inductance is that these inductive traces radiate EMI. For example, look at the traces with a near-field H probe close to the inductive traces (see Figure 7).
The frequency spectrum shows the rich radiated spectral content. The near-field probe starts to fall off at about 1GHz, so the harmonics are likely extend out to about 5GHz (as seen in the voltage across the 1Ω sense resistor).
We have seen that the edge speed of a very high speed CMOS logic gate can create harmonics to 5GHz or more. The 1Ω sense resistor allows us to get an indication of the transition energy of the device, though it does contribute to the peak-to-peak voltage. Eliminating the resistor would reduce the peak-to-peak voltage by approximately 220mV. Here are several ways to easily improve this issue:
1.The 1Ω sense resistor (of course) should be removed. It was only added in order to show the device transition current.
2.The decoupling capacitor should be moved to the right side of the chip very close to pin 5 (Vcc) of the logic gate
3.The capacitor ground should be connected to a bottom side ground plane under the device.
4.Use a low ESL ceramic decoupling capacitor and/or two parallel ceramic capacitors.
5.Switch to a multilayer PCB to reduce the distance between the signal trace and the groundplane.
