PCB Design Best Practices: Here’s what you need to keep in mind for net management and managing PCB layers. All the examples in this article are developed using the NI Multisim design environment, however the same concepts apply when using different EDA tools.
Net Management Best Practices
1. Perform Electrical Rules Checking
Running an electrical rules check (ERC) assists in quickly finding errors in the design, such as outputs tied together, improper connections to power or ground, and other incorrect wiring situations.
The ERC can also look for unconnected pins in the schematic as well. Occasionally, unconnected pins can get unnoticed (if wires are close to pins but not connected) and may inadvertently flow through to the layout stage.
2. Analyze the Netlist Report
Performing a netlist review can help find any human errors that may occur in net naming. Generate a Netlist report and sort the list by the‘net’column and look for any anomalies, such as single nets or incorrect net names that do not match desired naming conventions. As an example, a common error that can be easily avoided during this exercise is where a power signal is incorrectly assigned different names throughout a design. Consider a multipage schematic where a net is called 5VDC on one page but on another page, the power signal is incorrectly labeled 5V. If the original intent was to have a single 5VDC net connection, then if the discrepancy is left uncaught, the required 5VDC power signal would likely not be connected to IC parts on the page with the error, and this portion of the circuit would not function as designed.
PCB Management
1. Manage PCB Layers
In the schematic tool (NI Multisim software in our example), set the anticipated number of layers that the circuit board will have. (Additional layers can be added as required.) Keep in mind that it is easier to add layers rather than remove layers that already have placed copper.
Also the net-layer assignments will need to be set when initially transferring the design or whenever layers are changed within the design. The net-layer assignments will vary between designs, and users will need to consider separating the routing layers with signals with those for ground and power planes. However, most users can safely enable all net-layer assignments initially.
2. Manage Trace Width Settings
An acceptable default trace setting can be between 6 to 10 mils for most signal traces. A value of 10 mils is typical for most board designs, and thinner trace settings can be used for high-density boards. Trace widths need to be carefully considered for any special signal considerations, such as current carrying traces (wider power or ground traces to handle more current). A wider trace is typically set for higher currents. Also, larger trace-to-trace clearance settings need to be used for high-voltage signals to prevent arcing and for safety considerations. For quantitative data to be used based on the circuit’s design criteria, refer to the tables in IPC-2221, Generic Standard on Printed Board Design. During some of the semi-automatic and autorouting trace drawing modes, the algorithms may automatically decrease the width of the trace to fit the trace between pads, objects, or other traces. The trace min width setting can be used to prevent traces from getting too thin.
