1 Introduction
With the decrease of the volume of the system , improve the function of the operating frequency , the complexity of the system , which will require a number of different embedded modules simultaneously . Only the individual modules with good EMC and low EMI, in order to ensure the realization of the entire system functions. This not only requires a good system itself outside interference shielding properties, but also requires the presence of other systems simultaneously, can have serious EMI on the outside . In addition , switching power supply applications in high-speed digital system design more widely, a system often need to use a variety of power . Not only power systems vulnerable to interference, and noise generated by the power supply will give the whole system a serious EMC problems . Therefore, in high-speed PCB design, how to better filter out noise is the key to ensuring a good supply power integrity . This paper analyzes the capacitance of the filter characteristics , the effects of parasitic inductance of the capacitor capacitance filtering performance brings, as well as the phenomenon of PCB in the current loop , and then how to choose the bypass capacitor for making some conclusions . This paper also analyzes the generation mechanism of power supply noise and ground bounce noise and on its basis of bypass capacitors placed in the PCB in a variety of ways to make the analysis and comparison .
2 capacitor insertion loss characteristics , the frequency response characteristics of the filter characteristic capacitance
2.1 insertion loss characteristics ideal capacitor
EMI power filter for interference noise suppression capability is usually insertion loss (Insertion Loss) characteristics to be measured. Insertion loss is defined as: no access to the filter , the noise transmission from the noise source to the load power P1 and the access filter , the noise source to a noise power ratio P2 of the load , expressed in dB ( decibels ) . Figure 1 is the insertion loss characteristic of an ideal capacitor , it can be seen , 1μF capacitor corresponding to the slope of the curve close to the insertion loss 20dB/10 multiplier.
Wherein the observation of a characteristic of an insertion loss , as the frequency increases , the capacitance value of the insertion loss is increased , i.e. the value of P1/P2 is increased , which means that the system after the filter via a capacitor , it is possible to reduce the noise transmitted to the load, the ability to filter out high frequency noise enhancement capacitors . From the analysis of the ideal formula for capacitance , capacitance when a certain time , the higher the frequency , the lower loop impedance , that is easy to filter out high frequency components of the capacitor . From the two are the same conclusion .
Then observe different corresponding capacitance curve at a low frequency , the capacitance corresponding to various values of the insertion loss is approximately the same , but as the frequency increases , the insertion loss increases the amplitude of the small capacitance values of the capacitance larger slower , P1/P2 value will increase too slowly , that the large capacitance easier to filter out low frequency noise. Thus we have the high-speed circuit board design , usually placed in a 1 ~ 10μF capacitor power access terminal board , filter out low frequency noise ; between the power supply and ground for each device on the circuit board by placing a 0.01 to 0.1 μF capacitor filter out high frequency noise.
Impedance of the capacitor is connected between the power supply and ground can be calculated as follows: the aim is to filter capacitor filter superimposed on the AC component of the power system can be seen from the above formula , when a certain frequency , the greater the capacitance value , the smaller the impedance of the circuit , the easier it flows through the capacitor so that the AC signal ground plane up, in other words, the greater the filtering capacitor values seem better, in fact not the case , because the actual capacitance does not have All features ideal capacitance. The actual capacitance of the parasitic components , the structure of which is formed by the capacitor and the lead plate , and these components may be equivalent to the parasitic series resistance of the capacitor and inductor , often called the equivalent series resistance (ESR) and equivalent series inductance (ESL), the model shown in Figure 2, the left half of FIG . If you ignore the parasitic capacitance of the resistor then the model can be equivalent to the right part of Figure 2. This capacitor is actually a series resonant circuit. In the actual circuit or PCB design, the presence of parasitic inductance capacitance capacitor filter performance will have a great impact , therefore the design of the system should choose a relatively small parasitic capacitance of the inductor .
2.2 High-frequency response characteristics of the actual capacitance
From 2.1 we know that the actual capacitance at work because of the presence of parasitic inductance , capacitance makes the series resonant circuit becomes a loop. Resonant frequency , wherein : L is the equivalent inductance ; C the actual capacitance. As shown in Figure 3, when the frequency is less than f0, the capacitance presented ; greater frequency f0, the inductance presented . Therefore , the capacitor is more like a band rejection filter instead of a lowpass filter. ESL and ESR of the capacitor is constructed by the capacitor and the dielectric material determined , regardless of capacitance . For high-frequency rejection and will not replace the same type of large-capacity capacitor and enhanced. The impedance of the capacitor of the same type in a larger capacity is less than the frequency f0, smaller than the impedance of the capacitor is small, however , when the frequency is greater than the f0, ESL is no difference between the two determines the impedance. Seen, in order to improve the high-frequency filter characteristic must be used for the capacitor has low ESL . A capacitor of any effective frequency range is limited, and a system for both low-frequency noise , but also high-frequency noise , it is generally parallel use of different types of capacitors to achieve a wider effective frequency range.
3 model to analyze the use of PCB capacitors in circulation problem
Power supply decoupling capacitor placement will have a huge current loop improperly printed circuit board. In order to reduce noise at high speed printed circuit board designs, there is a very important principle is : to reduce the area of signal current loop. In the past we used to consider only the starting point of the current flowing , Ways and end , but rarely consider the current return path . In the high-frequency circuits , power and ground is usually considered equivalent, and therefore out of the current return path route will form a current loop, current loop in which , due to various reasons, such as the parasitic inductance of the capacitor , PCB connection inherent inductance such that the loop impedance is not zero , this current will produce a potential difference flows through Yihuan , if the current is changing, then the radiation, the system interference. In order to supply filtering in the circuit design is often to add some of the bypass capacitor between the power supply and ground , increasing the bypass capacitor in the circuit has two main purposes , firstly, to increase the ability to store charge in the loop , so the moment current is too large , resulting in ground bounce noise. Second, the proper placement of bypass capacitors , the circuit can be provided near the noise signal to reduce the area of the current loop , thereby reducing the loop inductance. A feedthrough capacitor in a circuit , the noise frequency is usually want to filter out high frequency AC signal , and thus such a circuit will still radiate outside . In order to reduce this radiation, we need to reduce the impedance of the loop as far as possible , must be reasonable to place the bypass capacitor. Figure 4 shows the filter capacitor due to improper placement generated large current loop .
Figure 5 is a model of the current loop . From the current loop model , we can see the presence of parasitic inductance loop, the state of their performance in the high frequency impedance of the loop power supply can cause spikes generated , and thereby radiate electromagnetic interference with other parts of the system . Ll loop capacitive pinouts package inductance ; Lpc capacitive device pins to PCB transmission line between the power or ground pins parasitic inductance ; Lic pinouts for the device parasitic inductance. In addition, we have discussed in the previous capacitor itself has parasitic inductance of ESL . The total inductance of the loop such as : L = 2Ll + 2Lpc +2 Lic + ESL. Because of the parasitic inductance of the loop would cause interference to the entire system, resulting in a voltage spike , the peak value of this voltage is a relationship between the presence of the same series inductance , the following approximate formula :
Where V is the maximum noise voltage spikes value , △ t is transient duration , △ I transient current for the device , △ t, △ I can look up the value from the device manual. For example 74HC typical transient current Icc of 20mA, the output signal rises from zero to Icc Icc or fall from time zero to the need for 4ns, if now we are trying to control inductive noise spikes less than 100mV, then the above formula we series inductance L can be obtained is not more than the maximum value of 20nH. PCB board design, the designer can be several ways to reduce loop inductance : Select parasitic inductance of the capacitor is relatively small , reducing ESL ( different types of parasitic inductance capacitance values in Table 1 ) ; possible to reduce the use of chip capacitors capacitor lead length , reducing Ll value ; reasonable placing capacitors , using power planes or ground plane layer instead of the power supply or transmission lines , reducing the power transmission line inductance Lpc; reasonable choice integrated device packaging to reduce Lic value , such as for devices ADV478 speaking , PLCC package parasitic inductance than the DIP package parasitic inductance smaller 2nH to 3nH.
4 power disturbances and ground bounce noise generation mechanism
Figure 6 is a simple totem pole I / O interface circuit , driving a tandem source matching transmission lines. The figure for the package inductance LG LV and device power pin and ground pin , A, B two FET used as a switch . Assuming the initial voltage and current at each point in time the transmission line are zero , at some point the device will drive the transmission line is high , this time the device needs to sink current from the power supply pins . At time t1, closing the switch A, the current flow from VCC PCB board flowing through package inductance LV, across the switch A, series termination resistors , and then flows into the transmission line, the amplitude of the output current (1/2) VCC/Z0. Current in the transmission line network for one full cycle (round-trip) time ends at time t2 . After this point , the full charge state in the transmission line , no additional current flowing to maintain. Chung had moments when the current package inductance LV, will lead to disturbances in the chip voltage at node V1 . At time t3, the switch off A, this action does not cause the generation of impulse noise , because the moment of opening of the switch A is no current flowing . Meanwhile, the switch is closed B, then the transmission line , the ground plane , package inductance LG and switch B Ring Road formed with instantaneous current flowing through the switch B, so that the node G1 disturbance generated at ground bounce . If between V1 and G1 plus a bypass capacitor ( placed on chip ) , then you can make the point of the transient voltage V1 and G1 disturbance at the same point , so every time switching , V1 and G1 points are points will produce a voltage disturbance , but the magnitude will be halved .
In high-speed PCB design, power pin is placed in the vicinity of the filter capacitor is to eliminate power disturbances and ground bounce noise. After the system with a bypass capacitor , the capacitance of the parasitic inductance present, the total inductance of the loop increases , the intensity of the noise is also likely will be greater . Therefore, the choice of the designer should be as small parasitic inductance bypass capacitor and a reasonable place it in the PCB .
5 device power pin bypass capacitor placement
When the current flowing into the device through the device in an instant power supply pin or pins into the ground through the ground , due to the presence of the device package inductance and power supply loop inductance exists , will have the power and ground bounce noise disturbance , and therefore need to supply placed near the pin in order to achieve the elimination of the power supply filter capacitor and ground bounce noise disturbances purpose .
From the above , the power and ground bounce noise disturbance mainly from the chip pins , because the output impedance of the chip ( the chip 's power or ground pin output impedance ) is generally much larger than the impedance of the power plane or ground plane ( If not , it will have a lot of power, ground noise ) , so the chip can be seen as a source of noise for a rational design of the circuit board is concerned , no matter what time , when the impedance of the noise source is greater than the load much of the time, the noise source can be considered as a current source , it will sink a certain amount of current to the power supply or the ground system. In order to reduce the power or ground noise , we need to take measures to reduce the power or ground plane poured into which the amount of current . In order to effectively do this, in theory, power or ground pins need to be connected in series with an impedance , the impedance must be large enough , the best output impedance than the chip power ground pin is also great. But such a large series impedance is unrealistic , because if so, will generate greater inside the chip ground bounce noise or power disturbances , resulting chip does not work properly. Therefore, the correct approach should be to try to lead through the noise to a low impedance ground plane loop up . The usual practice is to add the power pins of the chip bypass capacitor . Following is a brief analysis of the four capacitor placement .
8 (a) as shown in Figure 7 and , as a bypass capacitor placement . The chip 's ground pin directly through a low impedance vias D ( parasitic inductance vias generally about 1 ~ 2nH) is connected to the ground plane , ground bounce noise so the ground pin on the chip through vias flows into on the ground plane , inhibiting the effects of ground bounce noise on the chip. The chip 's power pins through a short transmission line ( usually about 50 ~ 80mil long , the parasitic inductance of about 1 ~ 1.6nH) is connected to the power supply capacitor plate pad , capacitive power disc pads and pad sites connected directly to the power supply through vias on the plane and the ground plane , so between the power pins to the ground plane will also have a low impedance path , effectively overcome the effects of power supply noise on the power supply pins on the chip. Meanwhile noise bypass capacitor near the power supply layer through vias also B, the bypass capacitor C via a low impedance path so that the inflow to the ground plane , so that effectively inhibit the placement of the chip and the power supply noise and Effect of other systems.
FIG 8 (b) , the through hole B in the capacitance between the power supply pin and the pin chips , which would increase the inductance of the loop path A , when the capacitance and at the same level when the chip is not generally used in this ways.
Figure 8 (c) , the capacitance of the power supply pin of the change via B hit close to the chip power pins at A , which placed a manner similar to the above-mentioned second placement will cause the loop inductance increases, this approach should be avoided.
FIG 8 (d) as shown to remove the pin and the power transmission line capacitance between the chip power supply pin , and the pin is connected directly to the chip supply through vias to a ground plane , a capacitive power supply pin and power pin of the chip inter- connected by a large power planes together , so path a includes : two vias , a power plane , a capacitor , also increases the loop inductance and noise power plane will bring unpredictable effects , in addition also increased the number of vias , reducing the wiring area of the board . This approach should also be avoided.
6 Conclusion
The current board-level digital systems with increasing frequency , various EMI problems are more serious. Rational selection and use of bypass capacitors is to eliminate EMI, get a key aspect of the power integrity. Moreover , with the further development of semiconductor technology , capacitors are upgrading to meet the different requirements of the high-speed circuit design . Therefore , the bypass capacitor selection, placement of bypass capacitors and other issues need to constantly discuss in depth .
