I. Introduction
With the gradual improvement PCB design complexity , for signal integrity analysis in addition to reflections, crosstalk and EMI, stable and reliable power supply designers have also become one of the key research direction . Especially when increasing the number of switching devices , decreasing the core voltage when the power fluctuations will tend to bring the deadly impact of the system , so people put forward a new noun : power integrity , referred to as PI (powerintegrity). Today's international market , IC design is relatively developed, but power integrity design is still a weak link. Therefore, this paper produced PCB board power integrity issues , analyzes the factors that influence and power integrity optimization method is proposed to solve the PCB board design and experience in power integrity issues , with a strong theoretical analysis and practical application value.
Second, analysis of the causes and power supply noise
For the cause of the power supply noise analysis we conducted through a NAND gate circuit diagram . Figure 1 is a block diagram of a circuit diagram of a three-input NAND gates , NAND gates as part of the digital device which is obtained by " 1" and " 0 " level to the switching of the work . With the increasing IC technology , the switching speed of digital devices faster and faster, which introduce additional high frequency component , and the inductance in the circuit is easy to cause the high frequency power supply fluctuations . As shown in Figure 1 , when the whole input NAND gate is high , the transistor circuit is turned on , the circuit instantaneous short circuit, power supply to the capacitor is charged , while the inflow ground . At this time due to the presence of parasitic inductance power and ground lines , we can see from the formula V = LdI / dt, which will generate voltage fluctuations in the power supply and ground lines , the rising level as shown in Figure 2 introduced ΔI noise. When NAND gate input is low , then the capacitor discharges , will have a greater ΔI noise on the ground line ; while the power at this time only momentary short circuit currents caused by mutations , since there is no charge to the capacitor leaving mutant relative to the rising edge of the current is small. From the NAND gate circuit of the analysis we know that the root causes of instability in the power lies mainly in two aspects: First, the device under high-speed switching, transient alternating current is too large ;
Second, the existence of the current loop inductance . The so-called ground power integrity problem is that in high-speed PCB , when a large number of chips simultaneously turned on or off , the circuit will produce a large transient currents , and because there is a power line and ground line inductance and resistance , it is will produce voltage fluctuations on both. Understand the nature of power integrity problem , we know that to solve the power integrity problem, first for high-speed devices , we are to get rid of it by adding high frequency noise components decoupling capacitor , thus reducing the transient time signal ; for the inductance present in the circuit , we designed the hierarchical power from consideration.
Third, the application of decoupling capacitors
In high-speed PCB design, decoupling capacitor plays an important role , its placement is also important. This is because the power supply to a load in a short time , prevent the charge stored in the capacitor voltage drops , such as a capacitor can not appropriate placement of the line impedance is too large, the impact power . Capacitance at the same time high-speed switching devices can filter out high frequency noise. Our high-speed PCB design in general, the power input and power output of each chip plus a decoupling capacitor , which generally larger capacitance values close to the power supply side ( eg 10μF), it is because we generally use the PCB is DC power supply, in order to filter capacitor resonant frequency power supply noise may be relatively low ; while the large capacitance can ensure the stability of the power supply output . Then the power pin for chip decoupling capacitors plus the premises , the value of its capacitance is generally small (e.g., 0.1μF), this is because the high-speed chip , the noise frequency is higher than normal , which requires added decoupling higher resonant frequency capacitance , i.e. the capacitance decoupling capacitor to be small.
For decoupling capacitor placement , we know that if the position properly, it will increase the line impedance , reducing its resonant frequency also affects supply. For chip decoupling capacitor and the inductor or power , we can by the formula : find
In the formula , l: line capacitance between the chips long ; r: Radius ; d: distance between the power line and the ground ;
Thus, we know that , to reduce the inductance L, the need to reduce l and d, i.e., to reduce the decoupling capacitors and the loop area formed by the chip , which is required as close to the chip and the chip capacitor device .
Fourth, the power supply circuit design
To ensure power integrity , we know that good power distribution network is essential. First, the design of power and ground , we want to ensure that the line width bold ( eg width 40mil, while the average signal line is 10mil), so as to reduce the impedance value as possible. With the increasing speed of the chip , according to the 5/5 rule, we are increasingly using plywood , for power and special formations form a loop through a dedicated power planes , thus reducing the line inductance.
Shown in Figure 4 is a signal diagram of a four-layer circuit board , the high frequency signal returned from the formation , the formation under ideal conditions ( no separation and excessive vias ) , a high-frequency signal line formed on the ground RF mirror circuit , the return current from the high frequency signal in the main return mirror in the path of the formation , and the PCB , the distance between the signal line and the ground is very small ( about 0.3mm), thus forming a small loop not only can reduce the power integrity issues , but also can reduce the loop RF radiation , electromagnetic compatibility to avoid other problems . But in today's highly integrated PCB design, due to the integrated chip is too high, too dense vias , power and ground planes separated by many factors such as power supply and analog and digital components caused by the coexistence , to ensure that the power supply circuit Barrier is difficult.
As shown in Figure 4 , the coexistence of digital devices and high-speed analog PCB , in order to prevent digital device brings high-frequency noise caused by the impact of analog , digital and analog we conducted a separate , discrete digital and analog ground with a 0 ohm resistor connected to the end with the power to form a loop through a little ground . This put the two parts of the digital-analog noise isolation , but also the introduction of a problem, due to the formation of separate undermine the continuity of the formation , hindering the small signal loop circuit , which makes the signal loop impedance increases , an increase of power integrity issues may arise , while the large loop also increases the return path loop electromagnetic compatibility and radio frequency radiation between the plates . In order to avoid these problems in digital devices and analog mixed layout we advocate a unified manner , that is, digital devices and analog partition layout , and to not be separated . Reasonable layout of the digital to analog devices , by Kirchhoff's laws we know , the high frequency circuit to return along the path of least impedance , which is the minimum loop area to return , the return path of digital devices and analog devices will also in the digital devices and analog return path corresponding to the mirror , do not cause interference between them.
For highly integrated PCB design, because the signal traces, may be more complex , the formation of the loop area may be relatively large . Figure 5 , the four-layer board , the letter line after a signal source ground and power planes from ground transport , and finally return to the top level . In the transmission path , the signal line loop formed by the high-frequency signal is very large . To solve this problem, we near the close of signal lines between the power and ground planes plus a capacitor. Thus , for high frequency signals, the signal lines on the top of the formation will result in a mirror circuit , and a signal line to generate the formation of a mirror layer on the power supply circuit , these two mirror circuit layer and the ground of the power supply capacitance form a loop between , so we try to use the power and ground planes as a loop , reducing the return loop area , thereby reducing the possibility to produce electromagnetic compatibility problems between power integrity and board.
V. Conclusion
Today's high-speed digital circuit design tends to complex design affects multiple power applications , reducing the power level , high- speed response and high sensitivity chip and PCB 's high level of integration brings the power integrity issues within the board more and more serious and widespread attention. Therefore, this paper through the power integrity analysis of the problem presented its generating factors , and to put forward some power integrity design method, which has a certain value for the optimization of PCB EMC design .
