With the viewpoint of electronics system design automation, a system design is usually divided into different levels of design processes. The effect of interconnect interface occurs when integrating different levels of designs. An unsuitable interface may cause poor performance for the whole system.
As a result, how to combine any two levels of designs is a major concern. In the information society era, the electronics industry has literally made great change to the world such as mobile applications laptop personal computers (PCs), even the nomadic digital cellular phones or personal digital assistants (PDA) deployed in our daily lives. One of the key technologies to make these products available is the electronics packaging and assembly technology. Packaging is a process of establishing interconnections, ranging from the naked die to single chip (or multichip) packaging, from single chip (or multichip) to PCB (or mother board), and finally from PCB to the whole system.
Different levels of packaging have their own automation tools, which are independent of each other. Just right the phenomenon, development of a cost-effective and integrated packaging tool is becoming more practical and important to tally with industrial requirements. The history of IC packages development has been a trend towards miniaturizing the weight and package dimension over time described in. This is the reason that IC packaging technology is improving rapidly in electronics industry.
PGA is a higher density package and has been widely used in the past couple of years. Lately many automated routers for PGA packages have been reported. Since high pin-count PGA packages require larger footprints when mounted on a PCB, this will significantly affect the PCB routability and performance. To our knowledge, the state-of-the-art PCB routers or package routers do not properly offer an integrated developing environment to consider the codesign between PCB routing and PGA package routing.
To supplement the missing link in electronic design automation, we describe a new codesign approach to realize the problem of PCB layout design. In this paper we shall extend the previous work to make a better pin assignment for a PGA package such that the nets routability of the PCB can be enhanced, where the meaning of pin assignment is realized that the pins location can be interchangeable. Figure 1 schematically shows the representation of the PCB routing and PGA package codesign, where I/O pins distributed on the substrate of a PGA package should be mounted on a PCB. The structure of a multilayer PGA package with containing a chip cavity, I/O pads and pins.
During the PCB routing, a net may start from one pin of the PGA package, and be routed to one or more terminal pins of other blocks on the PCB. In practical designs, a PCB can be addressed an individual system, such as a PC mother board, or just an interface card of a large system.
The proposed codesign approach is composed of three major phases: (1) PGA routing cost estimation; (2) PCB routing cost estimation; (3)and A simulated annealing (SA) technique is applied to find a better pin assignment solution for the PGA package according to the estimated costs of both the PGA package and PCB. In other words, we want to find a better one-to-one mapping from the pads to their corresponding pins on a package, hoping that we can increase the nets routability on a PCB. Once a better pin assignment of the PGA package has been made. The routing of PGA chip packaging and PCB detailed routing can separately be performed by using Chens router and Maze router based on three-dimensional operation, respectively.
