A printed-circuit board is like a multilayer sandwich of routing layers. In general, the current PCB technology offers as many as 30 or more routing layers. Referring to Figure 1, the PGA package and all other devices mounted on a PCB are called blocks. The pins of these blocks, excluding the I/O pins of package, are called terminal pins. Whereas I/O pins of the PGA package may go through all the routing layers within the footprint area because they are mounted onto the PCB by the pin-through-holes (PTH) technology.
The space in each routing layer that allows the routing wires to go through is called routing area, which may be divided into several sub-regions called routing regions. In the design of PCB, there may be a lot of obstacles distributed in the routing area. The routing wires connecting these terminal pins and I/O pins are called nets, and they can be routed in 45 or 90 degrees on any routing layer. The routing wires may also pass through the free space of the blocks underside as long as there is space to route. The wiring nets can change layers by using contacts.
For more convenience, the following symbols are defined and used in this paper for the development of codesign algorithm.
yk: the zone number, where k=1, 2, 3, and 4 stands for the left, top, right, and bottom zones, respectively, as shown in Figure 3. These four regions are used for the exchange of PGA pins in our algorithm.
yTki: the ith I/O pads in the kth zone.
yPki: the ith I/O pins in the kth zone. The order of the I/O pins is from the inner ring to the outer ring, as shown in Figure 2.
yTPi: the ith terminal pins of a block on a printed-circuit board.
yRj: the jth routing region on a printed-circuit board.
yBi: the ith blocks mounted on a printed-circuit board.
yN: the total number of I/O pins on a package, and also the total number of I/O pads on a naked die.
