A good layout to optimize efficiency , reduce thermal stress and to minimize noise and line of action and go between the components . It all stems from the designer in the current conduction path for power and signal flow understanding.
When a prototype power board power is first applied , the best case is that it can not only work, but also quiet , low heat. However, this situation is rare .
A common problem with switching power supply is " unstable" switching waveforms . In some cases, the jitter in the sound wave band , the magnetic element will generate audio noise. If the problem lies in the layout of the printed circuit board , to find out the reasons may be very difficult. Therefore, the correct PCB layout switching power supply design early on is critical.
Power supply designers to have a good understanding the technical details , as well as the functional requirements of the final product . Therefore , a circuit board design project from the beginning , critical power supply designers should layout, and PCB layout designers work closely .
A good layout can be optimized for power efficiency , reduce the thermal stress ; more importantly , it minimizes the noise, and take the line and the interaction between the components . To achieve these goals , the designer must understand the internal switching power supply current conduction path and signal flow . To achieve the correct non-isolated switching power supply layout, be sure to keep in mind the following design elements .
Layout Plan
A large embedded circuit board dc / dc power supply , to get the best voltage regulation, load transient response and efficiency of the system , we must make the power output close to the load device to minimize interconnect impedance PCB traces and conduction drop. Ensure that there is good air flow , limiting thermal stress ; using forced air cooling measures if they can , they have the power position near the fan .
In addition , a large passive components ( such as inductors and electrolytic capacitors ) are not allowed to block the air flow through the low surface mount semiconductor components, such as power MOSFET or PWM controller. In order to prevent the switching noise in the analog signal system , should be avoided as far as possible under the power line laying sensitive signal ; Otherwise, an internal ground layer to be placed between the power supply layer and the small signal layer mask used .
The key is to be in the early stages of system design and planning , the planning position in the power , and the need for board space . Sometimes designers will ignore this advice , but to focus on the large-scale system board that are more "important" or " exciting " circuit . Power management is seen after the work , just the power of extra space on the circuit board , this approach for efficient and reliable power supply design is very unfavorable .
For MLB, is a good way between the high current power devices sensitive layer and layer of small signal traces laying DC or DC input / output voltage level . Stratum or layer provides a DC voltage signal traces shield small exchanges to make it go from high noise interference power lines and power components.
As a general rule , multi- layer PCB board ground layer or DC voltage should not be separated . If this separation is inevitable , it is necessary to minimize the number of these layers and length of traces and trace wiring should maintain the same direction with a large current , so that the impact is minimized.
Figures 1a and 1c , respectively six and four- layer structure performing the switching of the power supply PCB . These small signal layer structure is sandwiched between the large- current power and ground planes , thus increasing the coupling between the high current / voltage and the analog power level of the small-signal capacitance of the noise level .
Figure 1b and 1d , respectively, six and four-story structure is a good PCB design helps minimize noise coupling between layers , strata for small signal shielding layer . The point is : we must put next to the outer layer of the power stage a ground layer , the outer layer of high-current power to use thick copper to minimize the PCB conduction loss and thermal resistance.
The layout of the power stage
Switching power supply circuit can be divided into two parts, power stage and small signal control circuitry. Power stage circuit includes components for the transmission of high-current , under normal circumstances , would be the first deployment of these components , and then on some particular point layout laying small signal control circuitry.
High current traces should be short and wide to minimize PCB inductance , resistance and voltage drop. For those with high di / dt pulse current alignment is particularly important in this regard .
Figure 2 shows a synchronous buck converter in a continuous current path and the pulse current path , a solid line indicates a continuous current path , the dotted line represents the pulse ( switch ) current paths. Pulse current path includes the following components connected to traces on : input decoupling ceramic capacitor CHF; upper control FET QT; and the lower synchronous FET QB, there is the option of connecting parallel Schottky diode.
PCB Design
Non-isolated switching power supply PCB layout considerations
A good layout to optimize efficiency , reduce thermal stress and to minimize noise and line of action and go between the components . It all stems from the designer in the current conduction path for power and signal flow understanding.
When a prototype power board power is first applied , the best case is that it can not only work, but also quiet , low heat. However, this situation is rare .
A common problem with switching power supply is " unstable" switching waveforms . In some cases, the jitter in the sound wave band , the magnetic element will generate audio noise. If the problem lies in the layout of the printed circuit board , to find out the reasons may be very difficult. Therefore, the correct PCB layout switching power supply design early on is critical.
Power supply designers to have a good understanding the technical details , as well as the functional requirements of the final product . Therefore , a circuit board design project from the beginning , critical power supply designers should layout, and PCB layout designers work closely .
A good layout can be optimized for power efficiency , reduce the thermal stress ; more importantly , it minimizes the noise, and take the line and the interaction between the components . To achieve these goals , the designer must understand the internal switching power supply current conduction path and signal flow . To achieve the correct non-isolated switching power supply layout, be sure to keep in mind the following design elements .
Layout Plan
A large embedded circuit board dc / dc power supply , to get the best voltage regulation, load transient response and efficiency of the system , we must make the power output close to the load device to minimize interconnect impedance PCB traces and conduction drop. Ensure that there is good air flow , limiting thermal stress ; using forced air cooling measures if they can , they have the power position near the fan .
In addition , a large passive components ( such as inductors and electrolytic capacitors ) are not allowed to block the air flow through the low surface mount semiconductor components, such as power MOSFET or PWM controller. In order to prevent the switching noise in the analog signal system , should be avoided as far as possible under the power line laying sensitive signal ; Otherwise, an internal ground layer to be placed between the power supply layer and the small signal layer mask used .
The key is to be in the early stages of system design and planning , the planning position in the power , and the need for board space . Sometimes designers will ignore this advice , but to focus on the large-scale system board that are more "important" or " exciting " circuit . Power management is seen after the work , just the power of extra space on the circuit board , this approach for efficient and reliable power supply design is very unfavorable .
For MLB, is a good way between the high current power devices sensitive layer and layer of small signal traces laying DC or DC input / output voltage level . Stratum or layer provides a DC voltage signal traces shield small exchanges to make it go from high noise interference power lines and power components.
As a general rule , multi- layer PCB board ground layer or DC voltage should not be separated . If this separation is inevitable , it is necessary to minimize the number of these layers and length of traces and trace wiring should maintain the same direction with a large current , so that the impact is minimized.
Figures 1a and 1c , respectively six and four- layer structure performing the switching of the power supply PCB . These small signal layer structure is sandwiched between the large- current power and ground planes , thus increasing the coupling between the high current / voltage and the analog power level of the small-signal capacitance of the noise level .
Non-isolated switching power supply PCB layout considerations
Figure 1b and 1d , respectively, six and four-story structure is a good PCB design helps minimize noise coupling between layers , strata for small signal shielding layer . The point is : we must put next to the outer layer of the power stage a ground layer , the outer layer of high-current power to use thick copper to minimize the PCB conduction loss and thermal resistance.
The layout of the power stage
Switching power supply circuit can be divided into two parts, power stage and small signal control circuitry. Power stage circuit includes components for the transmission of high-current , under normal circumstances , would be the first deployment of these components , and then on some particular point layout laying small signal control circuitry.
High current traces should be short and wide to minimize PCB inductance , resistance and voltage drop. For those with high di / dt pulse current alignment is particularly important in this regard .
Figure 2 shows a synchronous buck converter in a continuous current path and the pulse current path , a solid line indicates a continuous current path , the dotted line represents the pulse ( switch ) current paths. Pulse current path includes the following components connected to traces on : input decoupling ceramic capacitor CHF; upper control FET QT; and the lower synchronous FET QB, there is the option of connecting parallel Schottky diode.
Non-isolated switching power supply PCB layout considerations
Figure 3a shows a high di / dt current path PCB parasitic inductance. Due to the presence of parasitic inductance , the pulse current path will not only radiated magnetic field , and will produce a large voltage ringing and spikes on PCB traces and MOSFET. To minimize PCB inductance, pulse current loop when the minimum circumference have (so-called thermal loop ) deployment , which traces should be short and wide.
High frequency decoupling capacitors CHF should be 0.1μF ~ 10μF, X5R or X7R dielectric ceramic capacitor , it has an extremely low ESL ( effective series inductance ) and ESR ( equivalent series resistance ) . Larger capacitance of the dielectric (e.g., Y5V) may cause a large decrease in the capacitance values at different voltages and temperatures , and therefore is not the best material of CHF .
Figure 3b is a buck converter circuit provides a key of a pulse current layout example . To limit the number of resistors and the voltage drop via the power distribution components are placed on the same side of the circuit board , the power traces are also distributed on the same layer. When you need to go to a power cord other layers , to choose the path of a continuous current traces . When used to connect high-current loop hole in the PCB layers , use multiple vias to minimize impedance.
Figure 4 shows a boost converter circuit and the pulse current continuous current circuit . In this case, high-frequency ceramic capacitors should be placed close to MOSFET QB with CHF boost diode D output.
Figure 5 is a boost converter circuit layout example of the pulse current . At this point the key is to minimize the circuit by the switch QB, rectifier diode D and high-frequency output capacitance CHF formation.
Figures 6 and 7 ( slightly ) provides an example of a synchronous buck circuit , which emphasizes the importance of decoupling capacitors . Figure 6a is a biphasic 12VIN, 2.5VOUT/30A ( max ) of the synchronous buck power supply, the LTC3729 VOUT duplex single controller IC. When no load , the switch SW1 and SW2 of the node and the output inductor current waveforms are stable ( Figure 6b). However, if the load current exceeds 13A, the waveform start node SW1 loss period . The load current is higher , the problem will worsen ( Figure 6c).
Each channel at the input frequency increases two 1μF ceramic capacitors , we can solve this problem , isolate the thermal capacitance loop area of each channel , and make minimized. Even up to 30A maximum load current, the switching waveform remains stable.
High DV / DT switch region
Figures 2 and 4, the voltage swing SW VIN ( or VOUT) and ground with a high dv / dt rate. There are a wealth of high-frequency noise components on this node , is a powerful source of EMI noise . To minimize the switching nodes and other noise-sensitive capacitive coupling between the lines go , you may make SW copper area as small as possible . However, to a large inductor current conduction , and to provide cooling for the power MOSFET region , PCB SW junction region can not be too small. General recommendations at the switching node laying a ground copper area to provide additional shielding.
If the design is not used for the power MOSFET and the inductor for surface mounting of the radiator, the foil must have enough cooling area . For DC voltage nodes ( such as input / output voltage and power ground ) , a reasonable approach is to let the copper area as large as possible .
More vias help to further reduce thermal stresses. To determine the high dv / dt switching node suitable copper area , it is necessary to minimize the dv / dt noise associated with the ability to provide good heat dissipation MOSFET design to make a balance between the two .
Power Pad form
Note that the form of the power components of the pad , such as low ESR capacitors , MOSFET, diode and inductor. Figure 8a ( slightly ) and 8b ( slightly ) were given the power of irrational and rational form of component pads .
For decoupling capacitors , positive and negative vias should be as close to each other , in order to reduce the PCB ESL. This is particularly effective for low ESL capacitors . Small capacitance with low ESR capacitors are typically more expensive , incorrect form and poor alignment of the pads will reduce their performance , thereby increasing the overall cost. Typically , reasonable PCB to reduce noise in the form of pads , the thermal resistance is reduced , the pressure drop and minimizing the trace impedance and high current element.
There is a high current power components layout common misunderstanding when it is incorrectly using a hot pad (thermal relief), as shown in Figure 8a ( slightly ) below. Non- use hot pads if necessary , will increase the impedance of the power interconnection between components , resulting in higher power consumption and reduce the effect of small ESR decoupling capacitors . If the layout used in the large hole to conduction currents , make sure they have sufficient quantities to reduce impedance. Also, do not use hot pads to these vias.
Figure 9 ( omitted ) is a plurality of on-board power application, which share the same input supply voltage rail . When these supplies are not synchronized with each other , you need to input current traces isolate to avoid common impedance coupling noise between different power supplies. Each power supply has a local input decoupling capacitor is actually less critical .
For a single-output converters PolyPhase for each phase to make a symmetrical layout helps balance the thermal stress .
Layout Design Example
Figure 10 (a little ) is a design example, it is a 3.5V ~ 14V, maximum output 1.2V/40A duplex synchronous buck converter , using the LTC3855 PolyPhase current-mode buck controller stepper . Before starting PCB layout , a good habit is particularly marked in the logic diagram with different colors of high current traces , high noise high dv / dt traces , and sensitive small-signal traces. This chart will help designers to distinguish between the various PCB traces .
11 ( omitted ) is an example of the layout of the power level of the power supply member 1.2V/40A layer. Figure , QT is a high- side control MOSFET, QB is the low-side synchronous FET. QB optional increase contact area in order to get more output current. In the bottom of the power element layer , put a solid power formations .
The control circuit layout
The control circuit switch away from high noise copper area. Buck converter , a good approach is to be placed near the control circuit VOUT + side , while the boost converter control circuit will have close to VIN + end , let the power traces carry continuous current.
If you have a small space allows , control IC and power MOSFET and the inductor ( which are high-calorie high noise component ) between the distance ( 0.5 inches to 1 inch). If space is tight, forced to be placed close to the power MOSFET controller with inductive position , will have to pay particular attention to alignment with the ground or ground , the control circuit and power components to isolate.
Figure 12 (a little ) is a better solution in isolation LTC3855 power , IC with exposed pad GND should be soldered to the PCB, to minimize electrical resistance and thermal resistance. Decoupling capacitors should be a few key next to the IC pin.
Unlike the control circuit should have a separate signal power level ground ( analog ) ground. If you have a separate SGND ( signal ground ) and PGND ( power ground ) pin on the controller IC, should be separately cabling. For integrated MOSFET driver control IC, IC pin small- signal portion should be used SGND.
Between the signal ground and the power ground only one connection point. Reasonable approach is to return the signal to a clean point power formations . Only connect the two ground traces in the controller IC , you can achieve in two places. Figure 12 (a little ) gives recommendations LTC3855 power ground isolation method . In the present embodiment , IC with an exposed ground pad . This pad should be soldered to the PCB, to minimize electrical resistance and thermal resistance. Multiple vias should be placed in the ground pad area.
Control IC decoupling capacitors should be close to each pin. To minimize connection impedance , good method is to go directly to the decoupling capacitor pin , rather than through vias. Figure 12 ( a little ), the decoupling capacitors should be placed close to the LTC3855 pin is the current sense pin Sense + / Sense-, compensation pin ITH, signal ground SGND, the feedback divider feet FB, IC VCC voltage is cited foot INTVCC, as well as power ground pin PGND.
Loop area and crosstalk
Two or more adjacent conductors may be capacitively coupled. Conductor on a high dv / dt through the parasitic capacitance , on the other conductor coupling current. To reduce the power level control circuit coupled noise , high switching noise traces away from sensitive small- signal traces . If possible , to take the line and high noise sensitive traces on different layers of cloth and used as a noise shield internal stratigraphy .
Space permitting, the control IC to power MOSFET and inductor from a small distance (0.5 inch to 1 inch ) , which is both large noise and heat.
FET drive LTC3855 controller TG, BG, SW and BOOST pins have high dv / dt switching voltage. Connected to the most sensitive small-signal nodes LTC3855 pin is : Sense + / Sense-, FB, ITH and SGND. The sensitive signal traces near the time if the layout of the high dv / dt nodes, you must signal traces with high dv / dt go into a grounding wire or ground wire between the layers to shield noise.
When laying the gate drive signal , with short, wide traces to help minimize gate drive impedance path . In Figure 13 ( a little ) , the deployment of high- FET driver TG and SW traces should be minimal loop area to minimize inductance and high dv / dt noise. Similarly, the low FET drive traces BG to be close to a PGND traces.
If BG traces PGND under a layer of laying low FET AC ground return current path is automatically coupled to a close alignment of BG . AC current will flow minimum loop it finds / impedance. At this point, low gate drive does not require a separate PGND return traces. The best way is to try to reduce the number of layers through the gate drive traces , which prevents the gate noise propagation to other layers.
In all small signal traces , the current detection traces the most sensitive to noise . Volatility is typically less than the current detection signal 100mV, this noise is quite volatility . In LTC3855 for example , Sense + / Sense- alignment should be a minimum spacing of parallel deployment (Kelvin detection ) , in order to minimize the chance of picking di / dt related noise , as shown in 14 ( slightly ) below.
In addition, the filter resistor and capacitor current sensing traces should be as close to the IC pin. When a long test line noise injection , the effect of this structure is preferably filtered . If the inductor DCR current sensing mode with R / C network, the DCR sensing resistor R should be close to the inductor DCR sensing capacitance C and should be close to the IC.
If the traces to the vias using a Sense- return path , not via the contact layer other internal VOUT + . Otherwise, conductive vias may be large VOUT + currents generated by the voltage drop may undermine the current sense signal. To avoid high noise switching node (TG, BG, SW and BOOST traces ) laying near the current sense traces. If possible, the current sense traces and power levels where the layer formation is placed between the lines layer to go .
If the controller IC has a differential voltage remote sense pin , will have a positive , negative remote sense lines with independent alignment , but also a Kelvin sense connection .
Trace width selection
Specific controller pin , the current level and the noise sensitivity is unique, therefore, must choose a specific trace width for different signals. Typically , the small signal may be narrower network using 10mil ~ 15mil trace width. Large current network ( gate drive , VCC and PGND) should be used short, wide traces. Traces of these networks is recommended at least 20mil wide.
