In the design options to handle hundreds of Gbps serial link multiple printed circuit board made of a telecommunications switching subsystem is the key factor.
High-speed telecommunications switching subsystem contains multiple high-speed dense integrated circuits, integrated circuits in these different printed circuit board via a serial link several Gbit (eg: speed of 2.5Gbps of 512 I / O signal) interconnect together. The following constraints dense high speed printed circuit board design challenges:
● end signal integrity, proper termination and limited crosstalk - despite the packaging and connectors adverse effects;
● Each IC power consumption from 20W to 40W, with its instantaneous power supply current change capacity;
● by the hundreds of rising / falling to bypass that need careful handling 50 to 100ps synchronous switching device caused / decoupling;
● the same circuit board as many as four or five supply voltage (low voltage as low as 0.75 or 1.2V);
● different I / O level standard specific interfaces (such as LVPECL level of the clock, the serial link CML level, RAM interface HSTL / SSTL level and LVCMOS / TTL level);
● Quality clock / jitter (serial link requirements);
● reasonable device layout to meet the constraints of heat;
● printed circuit board materials, structures and cabling strategies;
● designed taking into account the cost of production, assembly and testing.
Understand the composition of the transmission medium
Transmission media usually contain driver / receiver integrated circuits, printed circuit board wiring and connectors of / backplane or midplane. Before starting the real wiring, careful analysis of some preliminary work is very important. The input and output of the circuit board wiring fastest optimal and worst-case simulation to determine the attenuation of the budget of the board. Structure of the system, an integrated circuit package I / O assignment and select the connector pins are layers of printed circuit boards has a direct relationship.
You also need to check all the wiring and classified. Number of various types of wiring board helps laminated best solution. Low frequencies (below 50MHz) signal lines can use any autorouter cloth at any level. IF (50 to 800MHz) signal line impedance must be distributed in a controlled lamellar, if you set the right tools and wiring delay matching is allowed crosstalk (parallel wiring for the longest length), automatic routing tools can complete its wiring.
High-speed signals, require special consideration (800MHz or more), such as 2.5Gbps, 5Gbps or 10Gbps signal traces must be distributed in a particular board layers. If such a large number of signal lines (e.g. 2.5Gbps signal has 1400 lines), which will determine the choice of the board material (according to decide whether to allow the selection of the attenuation budget loss materials), the laminated board selection (symmetric type coupling side, and the differential transmission lines of the strip) and vias.
Whether or not in the conventional through-vias (with loss of signal), to ensure a minimum number of vias and blind vias and micro-vias to reduce the thickness of the laminated board.
In considering these details, while you have to clear the board manufacturability and cost in mind. Circuit board material selection, configuration and policy board stacked vias will directly affect the cost, feasibility and performance of the circuit board thickness. In addition to considering the I / O number (including high speed in order to suppress the crosstalk of the additional quantity required), but also in board thickness, shape factor vias, the wiring style, and the distortion of the signal between the price of the connector selection a compromise, taking into account its insertion and extraction forces.
Power supply, power supply decoupling capacitors plane
The same board there are five or more power situation is not uncommon, this is due to the use of VLSI different vendors in different periods of development. Required for each power supply in-depth analysis to understand the minimum / maximum supply current, inrush current occurs when the situation requires it, the required accuracy, the expected noise characteristics (sources of noise, the largest peak and spectrum) and on sensitive to the effects of the circuit. The circuit board DC / DC voltage converter and noise-sensitive circuits together is not wise. Also need to consider the order of a voltage source, the output voltage characteristic in parallel, DC / DC voltage converter output, and the case when the hot-swappable.
Avoid over any medium / high-frequency signal lines split power planes or ground to avoid possible future EMC problems. Is defined in the circuit board closest to the power plane laminate in the inductance of the power supply decoupling capacitor vias to a minimum.
Any separation will bring a series capacitance parasitic inductance. For a given size of the capacitor package as small as possible selection (e.g.: 0402 instead of 0805), while reducing the distance through the hole and the pin or pad of the capacitor, the capacitance of a large copper solder pads, vias to maximize number distribution using buried capacitors. The decoupling capacitors integrated on the chip or module can maximize its effectiveness.
Difficult to ensure signal integrity
Before wiring board design layout, should be a key signal lines (clock and high-speed signal lines) to establish routing rules. Open area on the circuit board, it is easy to satisfy these rules, but the pads and vias of the BGA package and a connector pin number, difficult to apply these rules. Generating a large number of through-holes of the back pad large, which means that the actual impedance is different from the calculated reference plane based on the full value.
High-speed signals require controlled impedance signal transmission line for point to point, no signal and the signal line branch at the end of the signal line has terminated load. However, this assumption is difficult to guarantee. For all of these details, you should use approximate simulation model (Figure 1). Parameters of these models are based on the analog measuring your final application testing circuit boards and samples carried out to get. Analyzing current in the high-speed transmission line ground / power supply layer of the return path is very important. Speed of current return path is always through the minimum inductance path. One-off hole, the current return path becomes more complicated every pass. Requires careful consideration of the transmission line reference plane (power / ground) near the or each signal line vias.
For rising / falling 50 to 100 psec signal line, the only piece on the receiving end of the chip termination load. Due to the termination circuit board receiver chip exist within the package will generate leads branch signals, while the chip is often contain hundreds of such high-speed I / O pins.
Differential signal lines than the single-ended signal line noise immunity, the maximum rate of voltage change and a number of other factors have more advantages, but it must be properly applied to ensure the realization of these goals. Correct application means that when the source generates two completely inverted signal, a signal line at the other end, the receiver receives two signals can completely inverted. This situation means that if the driver-side work is not constant current consumption, you have to increase in order to ensure correct load rise time and fall time equal. This is exactly the same for the two signal lines (one is actually a mirror image of the other), they are given the length of the printed circuit board layers on the board must be identical. If you use a through-hole in the differential signal wiring, the through-hole must be placed at the same distance from the place where the drive end. Only the total length is equal to the signal line is not sufficient. Accurate differential line between A and B must end match
Met: the length of the signal line A = B signal line length in the X-plate layer on the sheet layer X - A signal line length in the Y plate signal line layer B = length in the Y plate layer. Empirically, most of the transmission of a printed circuit board material delay 7nsec / m or 7psec/mm.
After three circuit boards (source circuit board, backplane, circuit board receiving) the differential signal pair, if each circuit board has a mismatch of 1mm, then the receiving end there 21psec mismatch, in this case, if a transfer 50psec rising / falling edge of the differential signal at the receiving end would be difficult to obtain the appropriate threshold. At the same time you should also consider a connector used to transmit delay differential signal between two different pins.
Generally, today's high speed integrated circuit density than before the supply voltage is low. Our system includes 3.3V power supply circuit, and the circuit may be connected with 2.5V power supply; same board other circuits may be 1.8V or 1.5V power supply. Logic level may be LVPECL, CML, LVDS, HSTL, LVCMOS, etc. There is a big question board design is always that the receiver should be able to identify the driver of the logic level. The designer must design a "good" voltage conversion circuit to transmit information, while meeting the requirements of the transmission line and keep the rise and fall time of the signal.
EMC will also affect signal integrity and crosstalk. In order to minimize this effect, you can not make intermediate or high frequency signal through the slot from above or below the reference plane at, not to rich noise circuitry and noise-sensitive circuits together, for the entire board plus shielding ring, sensitive clock source as well. You must use the wiring layout tools you use to target all of the high-speed signal line parameters defined crosstalk.
Wiring board layout verification
Prior to the delivery of manufacturing printed circuit boards, you must carefully check the entire circuit board inspection should include:
● whether there is unnecessary signal branches, terminated the correct circuit board, the most appropriate decoupling (remember all the high-speed signals are buried layer of the circuit board, you will not be able to modify them);
● delay matching and crosstalk meet the requirements;
● exact mirror differential signal lines;
● shielding ring is placed;
● uniform distribution of the short-circuit is connected via the reference plane (the type of formation should be considered as a uniform copper layer);
● uniform minimum decoupling (you can use embedded capacitors, since they throughout the circuit board and exhibits minimal parasitic inductance).
CAD tools can be used for most interactive way to check the items listed above, which gives you the right DRC (design rule checking) guidelines.
Switch circuit board design half Tbit / sec of
Follow all of the above design principles in a single board design a 512Gbps switching circuit does not generate a signal integrity problems. 515x295mm board handle 32 ports routed 512Gbit data input and output, the packet consists of 64 to 80 bytes. It contains 20 layers of low loss epoxy board (Nelco N4000-13), a thickness of 3.2mm.
Board contains eight packet routing switch modules (624-pin BGA package); the control action from the microprocessor circuit; provides the clock for the clock circuit 8 and the switch modules 32-port adapter; DC / DC get the 1.8, 2.5 and 3.3V voltage converter from 248V conversion; 1200 signal I / O backplane connectors. Eight switching module in parallel, the switching circuit board 32 comprises input ports and 32 output ports. Each port consists of eight differential link to 2.5Gbps.
Overall, the panel included in the output link input link 2.5Gbps differential of 256 and 256 difference, the total length of 100cm (switching circuit boards, backplanes, adapter plate). Internal bus by the link 16 constitute 2.5Gbps links for each of the two switching module (circuit board total differential link 112 to 2.5Gbps).
The maximum power consumption of the circuit board is 200W, working in a range of 0-100 degrees. The maximum peak to peak noise is less than the 1.8V 40mV, maximum clock input of the clock and the clock input terminal of each switching module adapter jitter less than 35psec. Whether the few ports still running at full speed to run all 32 ports will happen deterioration of the eye (eye opening signal receiving end is always greater than 75%).
Designing such a board requires you to deal with a variety of areas, including the structure, logic and analog design system capabilities and limitations of the printed circuit board manufacturing and CAD tools, and so on.
