I have made project 2 layer PCB for PCB Design Contest,When other User try to order the message error PCB 3 Layer please fill order for L1, L2, L3, L4.This my project:https://www.pcbway.com/project/sh...
Hello,I am desiging a 4-layer RF board with 50 ohm impedence control for RF signals. I need the following information from pcbway before I finish up the layout and submit the order: 1) What...
Because many customers don't know the meaning of vias process on our website or choose them as default. So we always follow the gerber files to produce the vias to avoid mistake. This is our solut...
A basic PCB starts with a copper-clad fiberglass material or thin copper sheets adhered to either side of the board, as shown in Figure 1-5.Figure 1-5. Core material.With a multilayer board (a board...
Hi,I want to have microvias in my design but drilled vias would be 0.3mm, min trace width and clearance 5/5mil. Problem is that during order i have to select HDI in order to have microvia but then it ...
Rep: For no space V-cut, you just need to keep the copper trace with 0-0.5 MM space from the V-cut line.While for V-cut with space, the space need to be larger than 3MM and the min size of break-away ...
Rep:For panel by tab-route, we required 2MM space between single PCB and the connection place need to wider than 1.6MM. As the stamp hole on connection place need to be 0.45MM diameter and 0.35MM spac...
Rep:First of all,it is without extra cost for producing gold finger and beveling. If you need us to do beveling for you, please choose “Yes” on the following button. If you do not choose gold finger, ...
Because there are GPT/ GPB layer in the files,which shows the pointed place are pads with soldermask opening. Then our engineer think the pads should not cover by soldermask ,so they follow the GPT/GP...
It is because these holes are on the copper plane as below picture pointed by green arrow. Then the engineer mislead them as plated . Pls design these holes in the area which don't have coppe...
