New for version 2.0 (see video) are two universal EPROM sockets provide 2x2732, 2x2764, 2x27128, or 1x27256 EPROMs, one socketed on the board and the second in a ZIF for easy swap. Note that the memory map has changed from v1.x of the CPU board so programs will need to be re assembled/compiled. The v2.x memory map is on the schematic and user's manual on the project website.

The SBC-85 CPU board is a 100mm x 100mm 2-layer with a 120 pin edge connector (mechanically PCI). The serial SID and SOD lines, via a max232, offer a RS232 serial port for communication with a resident monitor or whatever you may decide to put in firmware. The 120 expansion bus includes power, all of the 8085 status and system signals, latched address bus, and many more unused terminals for future or other board-to-board signals.

RAM is provided by a 64-kBit 6264 and an additional 2kbit in the 8155. In addition to the additional RAM, the 8155 provides an onboard timer and 22 pins of I/O.

Power is provided by an external regulated 5V power supply through either the barrel connector or the backplane.

Other boards including the backplane, cassette interface, prototyping board, bus monitor are also available.

Please visit the project website for more details on the system including documentation.