Description

The V20-MBC2 is an easy to build V20HL CPU SBC (Single Board Computer). It follows the same "concept" of the Z80-MBC2 (https://hackaday.io/project/159973), with a SD as "disk emulator" and up to 1024KB RAM.

It has an optional on board 16x GPIO expander, and uses common cheap add-on modules for the SD and the RTC options. It has an "Arduino heart" using an Atmega32A as EEPROM and "universal" I/O emulator (so a "legacy" EPROM programmer is not needed).

It is compatible with the uTerm (https://hackaday.io/project/165325) and uCom (https://hackaday.io/project/165709) boards.

It is possible to use an 80C88 (CMOS version) too.

* * HARDWARE OVERVIEW * *

Here the V20-MBC hardware main specs:

- V20HL full static CMOS CPU (uPD70108H)

- can be used a 80C88 (CMOS version) too;

- RAM can be configured as 128/512/1024KB;

- optional RTC and microSD modules (the same used in the Z80-MBC2);

- optional 16x GPIO port;

- I2C expansion port;

- serial port;

- ISP connector (for the Atmega32);

- clock can be configured at 4/8MHz (by software).

The layout allows to "plug in" a uTerm or a uCom board as in the Z80-MBC2 (vertically or horizontally) using the same 3D printed brackets.

Please remember that a CMOS full static CPU is required here, so the only V20 CPU that can be used is the V20HL (uPD7108H, see the "H" at the end of the part code that makes the difference...).

Only this CMOS full static version allows to use a clock rate from DC and, under some conditions, guaranties that the logic levels are compatible with the Atmega32A ones (the Atmega-s logic input levels are not TTL compliant)

Another aspect of the V20-MBC is that the well known 8284 clock oscillator chip (normally used to generate the 8088/8086 clock with the required 33% duty cycle) is not used here. Reading the V20HL datasheet you can see that the -12 and -16 speed grades have a symmetrical clock requirement, and the -10 speed grade clock requirement can be met using a little lower clock with a 50% duty cycle (not greater than about 9MHz, so using a maximum 8MHz clock there is a good margin).

RAM CONFIGURATION

The V20-MBC allows three different RAM configurations:

• 128KB (1x128KB)
• 512KB (1x512KB)
• 1024KB (2x512KB)

To set the proper RAM configuration two jumpers (JP1/A19 and JP2/A17) must be set. This operation must be done when the board is not powered, and before the first power on with the RAM chips installed.

Please note that using a 128KB SRAM only the single SRAM chip configuration is supported (the 2x128KB is not supported).

The following table shows how to set jumpers JP1 and JP2 for the three RAM configurations:

Currently supported CP/M 2.2 (8080 mode) and CP/M-86:

All the updates and the details to build it (including the firmware for the Atmega32A and the SD image for HD emulation) are in the V20-MBC page here:

https://hackaday.io/project/170924